PIC16C641-04SLASHSP datasheet(67/136 Pages) MICROCHIP

67 / 136 page

Preliminary

DS30559A-page 67

PIC16C64X & PIC16C66X

9.5.1

RB0/INT INTERRUPT

The external interrupt on the RB0/INT pin is edge trig-

gered: either rising if bit INTEDG (OPTION<6>) is set,

or falling, if bit INTEDG is clear. When a valid edge

appears

the

RB0/INT

pin,

ﬂag

bit

INTF

(INTCON<1>) is set. This interrupt can be enabled/dis-

abled

setting/clearing

enable

bit

INTE

(INTCON<4>). The INTF bit must be cleared in soft-

ware in the interrupt service routine before re-enabling

this interrupt. The RB0/INT interrupt can wake-up the

processor from SLEEP, if bit INTE was set prior to

going into SLEEP. The status of the GIE bit decides

whether or not the processor branches to the interrupt

vector following wake-up. See Section 9.8 for details

on SLEEP and Figure 9-19 for timing of wake-up from

SLEEP through RB0/INT interrupt.

9.5.2

TMR0 INTERRUPT

An overﬂow (FFh

→ 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

enabled/disabled

setting/clearing

T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 6.0.

9.5.3

PORTB INTERRUPT

An input change on any bit of PORTB<7:4> sets ﬂag bit

RBIF (INTCON<0>). The interrupt can be enabled/dis-

abled

setting/clearing

enable

bit

RBIE

(INTCON<4>). For operation of PORTB (Section 5.2).

9.5.4

COMPARATOR INTERRUPT

See Section 7.6 for complete description of the com-

parator interrupt.

FIGURE 9-16: RB0/INT PIN INTERRUPT TIMING

OSC1

CLKOUT

INT pin

INTF ﬂag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

Interrupt Latency

PC+1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC+1)

Inst (PC-1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF ﬂag is sampled here (every Q1).

2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

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