PIC16C641-04SLASHSP datasheet(19/136 Pages) MICROCHIP

19 / 136 page

Preliminary

DS30559A-page 19

PIC16C64X & PIC16C66X

FIGURE 4-4:

PIC16C642/662 DATA

MEMORY MAP

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

PIR1

CMCON

INDF(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PIE1

PCON

VRCON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h

A0h

General

Purpose

7Fh

FFh

Bank 0

Bank 1

File

Address

Unimplemented data memory loca-

tions, read as '0'.

Note 1: Not a physical register.

2: Not implemented on the PIC16C642.

File

Address

PORTC

TRISC

PORTD(2)

TRISD(2)

PORTE(2)

TRISE(2)

General

Purpose

Mapped

in Bank 0

EFh

F0h

4.2.2

SPECIAL FUNCTION REGISTERS

The special function registers are registers used by the

CPU and Peripheral Modules for controlling the desired

operation of the device (Table 4-1). These registers are

static RAM.

The special function registers can be classiﬁed into two

sets (core and peripheral). The special function regis-

ters associated with the “core” functions are described

in this section. Those related to the operation of the

peripheral features are described in the section of that

peripheral feature.

PIC16C641-04/SP Datasheet(PDF) 19 Page - Microchip Technology

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