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PIC16C641-04/SP Datasheet(PDF) 18 Page - Microchip Technology |
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PIC16C641-04/SP Datasheet(HTML) 18 Page - Microchip Technology |
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18 / 136 page  PIC16C64X & PIC16C66X DS30559A-page 18 Preliminary © 1996 Microchip Technology Inc. 4.2 Data Memory Organization The data memory (Figure 4-4) is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected when bit RP0 (STATUS<5>) is cleared. Bank 1 is selected when the RP0 bit is set. The Special Function Regis- ters are located in the first 32 locations of each Bank. Register locations A0h-EFh (Bank 1) are general pur- pose registers implemented as static RAM. Some spe- cial function registers are mapped in Bank 1. 4.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 176 x 8 for the PIC16C642/662, and 128 x8 for the PIC16C641/661. Each is accessed either directly, or indirectly through the File Select Register FSR (Section 4.5). FIGURE 4-3: PIC16C641/661 DATA MEMORY MAP INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PIR1 CMCON INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC PIE1 PCON VRCON 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh 20h A0h General Purpose Register General Purpose Register 7Fh FFh Bank 0 Bank 1 File Address BFh C0h Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: Not implemented on the PIC16C641. File Address PORTD(2) TRISD(2) TRISE(2) PCLATH INTCON PORTE(2) PCLATH INTCON Mapped in Page 0 EFh F0h |
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