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PIC16C641-04/SP Datasheet(PDF) 59 Page - Microchip Technology |
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PIC16C641-04/SP Datasheet(HTML) 59 Page - Microchip Technology |
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59 / 136 page ![]() © 1996 Microchip Technology Inc. Preliminary DS30559A-page 59 PIC16C64X & PIC16C66X 9.3 Reset The PIC16CXXX differentiates between various kinds of reset: a) Power-on reset (POR) b) MCLR reset during normal operation c) MCLR reset during SLEEP d) WDT reset (normal operation) e) Brown-out Reset (BOR) f) Parity Error Reset (PER) Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset state” on Power-on reset, MCLR, WDT reset, Brown-out Reset, Parity Error Reset, and on MCLR reset during SLEEP. They are not affected by a WDT wake-up, since this is viewed as the resumption of nor- mal operation. TO and PD bits are set or cleared differ- ently in different reset situations as indicated in Table 9-4. These bits are used in software to determine the nature of the reset. See Table 9-6 for a full descrip- tion of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 9-7. The MCLR reset path has a noise filter to detect and ignore small pulses. See Table 12-6 for pulse width specification. FIGURE 9-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT S R Q External Reset MCLR/ VDD OSC1/ WDT Module VDD rise detect OST/PWRT On-chip(1) RC OSC WDT Time-out Power-on Reset OST PWRT Chip_Reset 10-bit Ripple-counter Enable OST Enable PWRT SLEEP See Table 9-3 for time-out situations. Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. Brown-out Reset BODEN CLKIN Pin VPP Pin 10-bit Ripple-counter Program Memory Parity MPEEN |
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