KAI-2001 datasheet(5/36 Pages) ONSEMI

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KAI−2001

www.onsemi.com

Vertical to Horizontal Transfer

Figure 4. Vertical to Horizontal Transfer Architecture

Top View

Direction of

Vertical

Charge

Transfer

Photodiode

Transfer

Gate

Fast

Line

Dump

H1S

Direction of

Horizontal

Charge Transfer

Lightshield

Not Shown

When the V1 and V2 timing inputs are pulsed, charge in

every pixel of the VCCD is shifted one row towards the

HCCD. The last row next to the HCCD is shifted into the

HCCD. When the VCCD is shifted, the timing signals to the

HCCD must be stopped. H1 must be stopped in the high state

and H2 must be stopped in the low state. The HCCD

clocking may begin tHD

ms after the falling edge of the V1

and V2 pulse.

Charge is transferred from the last vertical CCD phase into

the H1S horizontal CCD phase. Refer to Figure 27 for an

example of timing that accomplishes the vertical to

horizontal transfer of charge.

If the fast line dump is held at the high level (FDH) during

a vertical to horizontal transfer, then the entire line is

removed and not transferred into the horizontal register.

KAI-2001 Datasheet(PDF) 5 Page - ON Semiconductor