KAI-2001 datasheet(6/36 Pages) ONSEMI

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KAI−2001

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Horizontal Register to Floating Diffusion

Figure 5. Horizontal Register to Floating Diffusion Architecture

H2B

H1B

H2S

H2B

H1S

H1B

H1S

Floating

Diffusion

n (burried channel)

p (GND)

n (SUB)

n−

The HCCD has a total of 1,648 pixels. The 1,640 vertical

shift registers (columns) are shifted into the center 1,640

pixels of the HCCD. There are 4 pixels at both ends of the

HCCD, which receive no charge from a vertical shift

pixels (containing no electrons). The next 16 clock cycles

will contain only electrons generated by dark current in the

VCCD and photodiodes. The next 1,608 clock cycles will

contain photo-electrons (image data). Finally, the last 16

clock cycles will contain only electrons generated by dark

current in the VCCD and photodiodes. Of the 16 dark

columns, the first and last dark columns should not be used

for determining the zero signal level. Some light does leak

into the first and last dark columns. Only use the center 14

columns of the 16 column dark reference.

When the HCCD is shifting valid image data, the timing

inputs to the electronic shutter (SUB), VCCD (V1, V2),

and fast line dump (FD) should be not be pulsed. This

prevents unwanted noise from being introduced. The HCCD

is a type of charge coupled device known as a pseudo-two

phase CCD. This type of CCD has the ability to shift charge

in two directions. This allows the entire image to be shifted

out to the video L output, or to the video R output (left/right

image reversal). The HCCD is split into two equal halves of

824 pixels each. When operating the sensor in single output

mode the two halves of the HCCD are shifted in the same

direction. When operating the sensor in dual output mode

the two halves of the HCCD are shifted in opposite

directions. The direction of charge transfer in each half is

controlled by the H1BL, H2BL, H1BR, and H2BR timing

inputs.

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