KAI-2001 datasheet(7/36 Pages) ONSEMI

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KAI−2001

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Horizontal Register Split

Figure 6. Horizontal Register

Single Output

H2SL

H1SL

H1BL

H2SR

H1SR

H2BR

H1BR

Pixel

824

Pixel

825

H2SL

H2BL

H1BL

H2SL

H1SL

H1BL

H2SR

H1SR

H2BR

H1BR

Pixel

824

Pixel

825

H2SL

H2BL

H1BL

Dual Output

Single Output Operation

When operating the sensor in single output mode all pixels

of the image sensor will be shifted out the Video L output

(pin 31). To conserve power and lower heat generation the

output amplifier for Video R may be turned off by

connecting VDDR (pin 24) and VOUTR (pin 24) to GND

(zero volts).

The H1 timing from the timing diagrams should be

applied to H1SL, H1BL, H1SR, H2BR, and the H2 timing

should be applied to H2SL, H2BL, H2SR, and H1BR. In

other words, the clock driver generating the H1 timing

should be connected to pins 4, 3, 13, and 15. The clock driver

generating the H2 timing should be connected to pins 5, 2,

12, and 14. The horizontal CCD should be clocked for 4

empty pixels plus 16 light shielded pixels plus 1,608

photoactive pixels plus 16 light shielded pixels for a total of

1,644 pixels.

Dual Output Operation

In dual output mode the connections to the H1BR and

H2BR pins are swapped from the single output mode to

change the direction of charge transfer of the right side

horizontal shift register. In dual output mode both VDDL

and VDDR (pins 25, 24) should be connected to 15 V.

The H1 timing from the timing diagrams should be applied

to H1SL, H1BL, H1SR, H1BR, and the H2 timing should be

applied to H2SL, H2BL, H2SR, and H2BR. The clock driver

generating the H1 timing should be connected to pins 4, 3,

13, and 14. The clock driver generating the H2 timing should

be connected to pins 5, 2, 12, and 15. The horizontal CCD

should be clocked for 4 empty pixels plus 16 light shielded

pixels plus 804 photoactive pixels for a total of 824 pixels.

If the camera is to have the option of dual or single output

mode, the clock driver signals sent to H1BR and H2BR may

be swapped by using a relay. Another alternative is to have

two extra clock drivers for H1BR and H2BR and invert the

signals in the timing logic generator. If two extra clock

drivers are used, care must be taken to ensure the rising and

falling edges of the H1BR and H2BR clocks occur at the

same time (within 3 ns) as the other HCCD clocks.

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