L8708H datasheet(53/66 Pages) ZILOG

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Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

DS96LV00800

P R E L I M I N A R Y

WDT Time Select (D0, D1). Selects the WDT time period.

It is configured as shown in Table 8.

WDTMR During HALT (D2). This bit determines whether

or not the WDT is active during HALT mode. A 1 indicates

active during HALT. The default is 1.

WDTMR During STOP (D3). This bit determines whether

or not the WDT is active during STOP mode. Since the

XTAL clock is stopped during STOP mode, the on-board

RC has to be selected as the clock source to the

WDT/POR counter. A 1 indicates active during STOP. The

default is 1.

Clock Source for WDT (D4). This bit determines which

oscillator source is used to clock the internal POR and

WDT counter chain. If the bit is a 1, the internal RC oscil-

lator is bypassed and the POR and WDT clock source is

driven from the external pin, XTAL1. The default configu-

ration of this bit is 0, which selects the RC oscillator.

Table 8. WDT Time Select

Time-Out of

Internal RC OSC

Time-Out of

XTAL Clock

5 ms min

256 TpC

10 ms min

512 TpC

20 ms min

1024 TpC

80 ms min

4096 TpC

Notes:

TpC = XTAL clock cycle.

The default on reset is 10 ms.

Figure 44. Resets and WDT

CLK

18 Clock RESET

Generator

RESET

* /CLR 2

WDT TAP SELECT

INTERNAL

OSC.

CLK

*CLR1

POR

WDT1

Low Operating

Voltage Det.

Internal

RESET

Active

High

CK Source

Select

(WDTMR)

XTAL

VDD

VBO/VLV

2V REF.

From Stop

Mode

Recovery

Source

WDT

Stop Delay

Select (SMR)

12 ns Glitch Filter

5 Clock

Filter

WDT/POR Counter Chain

/RESET

* /CLR1 and /CLR2 enable the WDT/POR and

18 Clock Reset timers upon a Low to High input translation.

VCC

L8708H Datasheet(PDF) 53 Page - Zilog, Inc.

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