DLPC910 datasheet(18/50 Pages) TI1

18 / 50 page

0100

4:1

SERDES Data

(at the interface)

½ Speed

System CLK

Full Speed

IO CLK

Output Data

0100

DLPC910

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

www.ti.com

Feature Description (continued)

Figure 4. Training Pattern Alignment

NOTE

In Xilinx FPGAs (due to the construction of the ISERDES and OSERDES cells) a pattern

of 0010 needs to be applied to the output/transmitting SERDES cells data pins (D1 = 0,

D2 = 0, D3 = 1, D4 = 0) in order to receive a result of 0100 (Q1 = 0, Q2 = 1, Q3 = 0, Q4 =

0) at the input/receiving SERDES cell.

The patterns should be applied on all of the data and DVALID pins. In this respect, the interface is treated as a

17 bit interface with DVALID being the 17th data bit. The receiving logic in the DLPC910 adjusts the clock phase

until the correct pattern is seen at the inputs. This allows DLPC910 to correctly select a clock phase for data

capture and will contribute to a more robust interface. It is important that the training pattern is applied to the

DVALID and data inputs of the DLPC910 before reset to the device is de-asserted, as training commences

immediately on the de-assertion of reset. The INIT_ACTIVE signal is asserted while the device is held in reset in

order to help facilitate this behavior.

7.3.5 Row and Block Interface

7.3.5.1 Row Mode

The DMD incorporates single row write operations using a row address counter that is randomly addressable.

ROWMD(1:0) determines the single row write count mode and ROWAD(10:0) determines the single row write

address. ROWMD and ROWAD must be asserted and de-asserted synchronously with DVALID. Row address

orientation depends on the North or South Flip Flag (NS_FLIP) input to the DLPC910. Refer to Related

Documentation for the DMD datasheet regarding orientation of rows, columns, and Mirror Clocking Pulse (MCP)

blocks. The row address counter does not automatically wrap-around when using the increment row address

pointer instruction. After the final row is addressed, the row address pointer must be cleared to 0.

7.3.5.2 Block Mode

The signals RST2BLKZ, BLK_MD and BLK_AD are used to designate which mirror block(s) is to be issued a

MCP or a Block Clear.

Submit Documentation Feedback

Product Folder Links: DLPC910

DLPC910 Datasheet(PDF) 18 Page - Texas Instruments