DLPC910 datasheet(20/50 Pages) TI1

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Data Sent

Data Loaded

DLPC910

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

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Prior to power removal, assert PWR_FLOAT and allow approximately 300

μs for the procedure to complete. This

procedure will assure the mirrors are in a flat state. Following this procedure, the power can be safely removed.

To restart after assertion of PWR_FLOAT, the DLPC910 must be reset by setting CTRL_RSTZ low (logic 0) for

50ms, and then back to high (logic 1), or power to the DLPC910 must be cycled.

To avoid leaving a static image on the DMD without removing power, a mirror FLOAT operation can be issued to

the DMD. A mirror FLOAT sequence begins by asserting the proper BLK_MD and BLK_AD as described in

Table 5. During the following row cycle, the DMD releases the tension under each mirror so that all mirrors are in

a relatively flat position. The FLOAT operation takes approximately 300

μs to complete, during which time

RST_ACTIVE is asserted. Normal operation may then continue without reseting or cycling power to the

DLPC910 or the DMD.

7.3.6.5 Load4

Load4 functionality provides improved global binary pattern rates for applications that can trade diminished

vertical resolution for higher pattern rates. Examples of these types of applications are shutter or chopper

applications and vertical structured light patterns. Asserting LOAD4_ENZ causes the attached DMD to load 4

rows for every row of data sent, reducing the pattern load time to ¼ of a full DMD load. It does not reduce the

MCP timing.

7.3.6.5.1

Load4 Row Addressing

In Load4 mode, automatic increment mode and row address mode can still be used as before, however the

largest addressable row will be (1600/4) - 1 = 399. The addressable vertical resolution is reduced by four,

although the physical resolution is unchanged.

Automatic increment address mode will automatically increment the row address input by one (or decrement by

one for N/S flip). The row address input will be re-mapped as shown in Table 3, where Vres = the vertical

resolution of the DMD.

Table 3. Load4 Row Address Mapping

ROW ADDRESS INPUT

PHYSICAL ROWS LOADED ON DMD

0, 1, 2, 3

4, 5, 6, 7

8, 9, 10, 11

12, 13, 14, 15

4N, 4N+1, 4N+2, 4N+3

(VRes/4) -1

VRes-4, VRes-3, VRes-2, VRes-1

Figure 5. Example Load4 Row Address Mapping

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