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DLPC910 Datasheet(PDF) 29 Page - Texas Instruments |
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DLPC910 Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 50 page ![]() Load Block 0 Load Block 1 Load Block 15 DIN_A/B/C/D BLK_MD/BLK_AD RST_ACTIVE { { { { Reset All Exposure Period Mirror Settling Time for All Blocks Load Block 0 Load Block 1 Load Block 15 Reset All { { { { Load Block 15 Load Block 0 DIN_A/B/C/D Reset Blocks 12-15 Reset Blocks 0-3 BLK_MD/BLK_AD RST_ACTIVE Load Block 2 Load Block 1 Mirror Settling Time for Blocks 12 - 15 Load Block 3 Load Block 4 Exposure Period Load Block 15 Load Block 0 DIN_A/B/C/D Reset Blocks 14-15 Reset Blocks 0-1 BLK_MD/BLK_AD RST_ACTIVE Load Block 1 Mirror Settling Time for Blocks 14 and 15 Exposure Period Load Block 2 DLPC910 www.ti.com DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015 Figure 11. Dual Block Load Phased Sequence Figure 12. Quad Block Load Phased Sequence Figure 13. Full DMD Global Load Sequence Note: After a MCP or Block Clear command is given, RST_ACTIVE may not be asserted until up to 60ns (depending on the clock frequency) after the command. While RST_ACTIVE is asserted, no other command should be given. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links: DLPC910 |
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