DLPC6401 datasheet(35/50 Pages) TI1

35 / 50 page

PLLM_

VSS

MOSC

VIA to Common Analog

Digital Board Power Plane

VIA to Common Analog

Digital Board Ground Plane

ASIC Pad

PCB Pad

Local

Decoupling

for the PLL

Digital Supply

Signal VIA

PLLD_

VSS

MOSC

PLLM_

VAS

PLLM_

VAD

PLLM_

VDD

PLLD_

VAS

PLLD_

VAD

PLLD_

VDD

MOSC

Crystal

Oscillator

10.0uF

DLPC6401

www.ti.com

DLPS031C – DECEMBER 2013 – REVISED AUGUST 2015

10 Layout

10.1 Layout Guidelines

TI recommends 2-ounce copper (2.6-mil) power and ground planes in the PCB design to achieve needed thermal

connectivity.

10.1.1 PCB Layout Guidelines for Internal ASIC Power

TI recommends the following guidelines to achieve desired ASIC performance relative to internal PLLs:

•

The DLPC6401 device contains two PLLs (PLLM and PLLD), each of which has a dedicated 1.2-V digital and

1.8-V analog supply. These 1.2-V PLL pins should be individually isolated from the main 1.2-V system supply

through a ferrite bead. The impedance of the ferrite bead should be much greater than that of the capacitor at

frequencies where noise is expected. Specifically the impedance of the ferrite bead must be less than 0.5

in the frequency range of 100 to 300 kHz and greater than 10

Ω in the frequency range >100 MHz.

•

As a minimum, 1.8-V analog PLL power and ground pins should be isolated using an LC-filter with a ferrite

serving as the inductor and a 0.1-µF capacitor on the ASIC side of the ferrite. TI recommends that this 1.8-V

PLL power be supplied from a dedicated linear regulator and each PLL should be individually isolated from

the regulator. The same ferrite recommendations described for the 1.2-V digital PLL supply apply to the 1.8-V

analog PLL supplies.

•

When designing the overall supply filter network, take care to ensure no resonance occurs. Particularly take

care around the 1- to 2-mHz band, as this coincides with the PLL natural loop frequency.

Figure 18. PLL Filter Layout

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