DLPC6401

www.ti.com

DLPS031C – DECEMBER 2013 – REVISED AUGUST 2015

Pin Functions (continued)

INTERNAL TERMINATION

CLK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

Requires an external pullup to

3.3 V. The minimum

I2C0_SCL

M2

VDD33

acceptable pullup value is 1

N/A

such as temperature sensor. This bus supports 400-

k

Ω. This input is not

kHz, fast-mode operation.

5-V tolerant.

Requires an external pullup to

3.3 V. The minimum

I2C0_SDA

M3

VDD33

acceptable pullup value is 1

I2C0_SCL

such as temperature sensor. This bus supports 400-

k

Ω. This input is not

kHz, fast-mode operation.

5-V tolerant.

SYSTEM CLOCK

System clock oscillator input (3.3-V LVCMOS). Note

MOSC

A14

VDD33

N/A

that the MOSC must be stable a maximum of 25 ms

after POSENSE transitions from high to low.

MOSCN

A15

VDD33

N/A

MOSC crystal return

P1A_CLK

W15

VDD33

Includes an internal pulldown

N/A

Port 1 input data pixel write clock 'A'

P1B_CLK

AB17

VDD33

Includes an internal pulldown

N/A

Port 1 input data pixel write clock 'B'

P1C_CLK

Y16

VDD33

Includes an internal pulldown

N/A

Port 1 input data pixel write clock 'C'

P1_VSYNC

Y15

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 vertical sync. Uses hysteresis

H

P1_HSYNC

AB16

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 horizontal sync. Uses hysteresis

H

P1_DATEN

AA16

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 data enable

Port 1 field sync. Required for interlaced sources

P1_FIELD

W14

VDD33

Includes an internal pulldown

P1A_CLK

only (and not progressive)

P1_A_9

AB20

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 A channel input pixel data (bit weight 128)

P1_A_8

AA19

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 A channel input pixel data (bit weight 64)

P1_A_7

Y18

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 A channel input pixel data (bit weight 32)

P1_A_6

W17

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 A channel input pixel data (bit weight 16)

P1_A_5

AB19

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 A channel input pixel data (bit weight 8)

P1_A_4

AA18

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 A channel input pixel data (bit weight 4)

P1_A_3

Y17

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 A channel input pixel data (bit weight 2)

P1_A_2

AB18

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 A channel input pixel data (bit weight 1)

P1_A_1

W16

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 A channel input pixel data (bit weight 0.5)

P1_A_0

AA17

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 A channel input pixel data (bit weight 0.25)

P1_B_9

U21

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 B channel input pixel data (bit weight 128)

P1_B_8

U20

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 B channel input pixel data (bit weight 64)

P1_B_7

V22

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 B channel input pixel data (bit weight 32)

P1_B_6

U19

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 B channel input pixel data (bit weight 16)

P1_B_5

V21

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 B channel input pixel data (bit weight 8)

P1_B_4

W22

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 B channel input pixel data (bit weight 4)

P1_B_3

W21

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 B channel input pixel data (bit weight 2)

P1_B_2

AA20

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 B channel input pixel data (bit weight 1)

P1_B_1

Y19

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 B channel input pixel data (bit weight 0.5)

P1_B_0

W18

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 B channel input pixel data (bit weight 0.25)

P1_C_9

P21

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 C channel input pixel data (bit weight 128)

P1_C_8

P22

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 C channel input pixel data (bit weight 64)

(3)

Port 1 can be used to support multiple source options for a given product (that is, HDMI, BT656). To do so, the data bus from both

source components must be connected to the same port 1 pins and control given to the DLPC6401 to tri-state the inactive source. Tying

them together like this causes some signal degradation due to reflections on the tri-stated path.

(4)

The A, B, and C input data channels of port 1 can be internally swapped for optimum board layout.

(5)

Sources feeding less than the full 10-bits per color component channel should be MSB justified when connected to the DLPC6401 and

LSBs tied off to 0. For example, an 8-bit per color input should be connected to bits 9:2 of the corresponding A, B, or C input channel.

BT656 are 8 or 10 bits in width. If a BT656-type input is used, the data bits must be MSB justified as with the other types of input

sources on either of the A, B, or C data input channels.

Copyright © 2013–2015, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Links: DLPC6401