DLPC6401

DLPS031C – DECEMBER 2013 – REVISED AUGUST 2015

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Pin Functions (continued)

INTERNAL TERMINATION

CLK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

P1_C_7

R19

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 C channel input pixel data (bit weight 32)

P1_C_6

R20

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 C channel input pixel data (bit weight 16)

P1_C_5

R21

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 C channel input pixel data (bit weight 8)

P1_C_4

R22

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 C channel input pixel data (bit weight 4)

P1_C_3

T21

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 C channel input pixel data (bit weight 2)

P1_C_2

T20

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 C channel input pixel data (bit weight 1)

P1_C_1

T19

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 C channel input pixel data (bit weight 0.5)

P1_C_0

U22

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 C channel input pixel data (bit weight 0.25)

Includes weak internal

Positive differential input signal for clock, FPD-Link

RCK_IN_P

Y9

VDD33_FPD

N/A

pulldown

receiver

Includes weak internal

Negative differential input signal for clock, FPD-Link

RCK_IN_N

W9

VDD33_FPD

N/A

pulldown

receiver

Includes weak internal

Positive differential input signal for data channel A,

RA_IN_P

AB10

VDD33_FPD

RCK_IN

pulldown

FPD-Link receiver

Includes weak internal

Negative differential input signal for data channel A,

RA_IN_N

AA10

VDD33_FPD

RCK_IN

pulldown

FPD-Link receiver

Includes weak internal

Positive differential input signal for data channel B,

RB_IN_P

Y11

VDD33_FPD

RCK_IN

pulldown

FPD-Link receiver

Includes weak internal

Negative differential input signal for data channel B,

RB_IN_N

W11

VDD33_FPD

RCK_IN

pulldown

FPD-Link receiver

Includes weak internal

Positive differential input signal for data channel C,

RC_IN_P

AB12

VDD33_FPD

RCK_IN

pulldown

FPD-Link receiver

Includes weak internal

Negative differential input signal for data channel C,

RC_IN_N

AA12

VDD33_FPD

RCK_IN

pulldown

FPD-Link receiver

Includes weak internal

Positive differential input signal for data channel D,

RD_IN_P

Y13

VDD33_FPD

RCK_IN

pulldown

FPD-Link receiver

Includes weak internal

Negative differential input signal for data channel D,

RD_IN_N

W13

VDD33_FPD

RCK_IN

pulldown

FPD-Link receiver

Includes weak internal

Positive differential input signal for data channel E,

RE_IN_P

AB14

VDD33_FPD

RCK_IN

pulldown

FPD-Link receiver

Includes weak internal

Negative differential input signal for data channel E,

RE_IN_N

AA14

VDD33_FPD

RCK_IN

pulldown

FPD-Link receiver

(6)

Port 2 is a single-channel FPD-Link compatible input interface. FPD-Link is a defacto industry standard FPD interface, which uses the

high-bandwidth capabilities of LVDS signaling to serialize video and graphics data down to a couple wires to provide a low-wire count

and low-EMI interface. Port 2 supports source rates up to a maximum effective clock of 90 MHz. The port 2 input pixel data must adhere

to one of four supported data mapping formats (see Table 2). Given that port 2 inputs contain weak pulldown resistors, they can be left

floating when not used.

6

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