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DLPC6401 Datasheet(PDF) 16 Page - Texas Instruments |
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DLPC6401 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 50 page  DLPC6401 DLPS031C – DECEMBER 2013 – REVISED AUGUST 2015 www.ti.com 6.10 Port 1 Input Pixel Interface Timing Requirements MIN MAX UNIT ƒclock Clock frequency, P1A_CLK, P1B_CLK, P1C_CLK 12 150 MHz tc Cycle time, P1A_CLK, P1B_CLK, P1C_CLK 6.666 83.33 ns tw(H) Pulse duration, high 50% to 50% reference points (signal) 2.3 ns tw(L) Pulse duration, low 50% to 50% reference points (signal) 2.3 ns Clock period jitter, P1A_CLK, P1B_CLK, P1C_CLK tjp Max ƒclock See (1) ps (that is, the deviation in period from ideal period) tt Transition time, tt = tf / tr, P1A_CLK, P1B_CLK, P1C_CLK 20% to 80% reference points (signal) 0.6 2 ns Transition time, tt = tf / tr, P1_A(9-0), P1_B(9-0) , P1_C(9- tt 20% to 80% reference points (signal) 0.6 3 ns 0), P1_HSYNC, P1_VSYNC, P1_DATEN Transition time, tt = tf / tr, ALF_HSYNC, ALF_VSYNC, tt 20% to 80% reference points (signal) 0.6 3 ns ALF_CSYNC(2) SETUP AND HOLD TIMES(3) tsu Setup time, P1_A(9-0), valid before P1x_CLK ↑↓ 0.8 ns th Hold time, P1_A(9-0), valid after P1x_CLK ↑↓ 0.8 ns tsu Setup time, P1_B(9-0), valid before P1x_CLK ↑↓ 0.8 ns th Hold time, P1_B(9-0), valid after P1x_CLK ↑↓ 0.8 ns tsu Setup time, P1_C(9-0), valid before P1x_CLK ↑↓ 0.8 ns th Hold time, P1_C(9-0), valid after P1x_CLK ↑↓ 0.8 ns tsu Setup time, P1_VSYNC, valid before P1x_CLK ↑↓ 0.8 ns th Hold time, P1_VSYNC, valid after P1x_CLK ↑↓ 0.8 ns tsu Setup time, P1_HSYNC, valid before P1x_CLK ↑↓ 0.8 ns th Hold time, P1_HSYNC, valid after P1x_CLK ↑↓ 0.8 ns tsu Setup time, P1_FIELD, valid before P1x_CLK ↑↓ 0.8 ns th Hold time, P1_FIELD, valid after P1x_CLK ↑↓ 0.8 ns tsu Setup time, P1_DATEN, valid before P1x_CLK ↑↓ 0.8 ns th Hold time, P1_DATEN, valid after P1x_CLK ↑↓ 0.8 ns (1) Use the following formula to obtain the jitter: Maximum clock jitter = ±[(1 / ƒclock) – 5414 ps]. (2) ALF_CSYNC, ALF_VSYNC and ALF_HSYNC are asynchronous signals. (3) Setup and hold times should be considered the same regardless of clock used [P1A_CLK, P1B_CLK, P1C_CLK]. 6.11 Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements (1) (2) (3) (4) (5) (6) MIN MAX UNIT ƒclock Clock frequency, P2_CLK (LVDS input clock) 20 90 MHz tc Cycle time, P2_CLK (LVDS input clock) 11.1 50 ns Clock or data slew rate (ƒpxck < 90 MHz) 0.3 V/ns tslew Clock or data slew rate (ƒpxck > 90 MHz) 0.5 V/ns tstartup Link start-up time (internal) 1 ms (1) Minimize crosstalk and match traces on the PCB as close as possible. (2) Maintain the common mode voltage as close to 1.2 V as possible. (3) Maintain the absolute input differential voltage as high as possible. (4) The LVDS open input detection is related to a low common mode voltage only. It is not related to a low-differential swing. (5) LVDS power 3.3-V supply (VDD33_FPD) noise level should be below 100 mVPP. (6) LVDS power 1.2-V supply (VDD12_FPD) noise level should be below 60 mVPP. 16 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DLPC6401 |
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