LNBH25S datasheet(11/37 Pages) STMICROELECTRONICS

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LNBH25S

Application information

DocID026736 Rev 2

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2.14

IMON (minimum output current diagnostic)

In order to detect the output load absence (no LNB connected on the bus or cable not

connected to the IRD) the LNBH25S is provided with a minimum output current flag by the

IMON I²C bit, accessible in read mode, which is set to “1” if the output current is lower than

12 mA (typ.). IMON function should be used with the 22 kHz tone transmission deactivated,

otherwise the IMON bit could be set to “0” even if the output current is below the minimum

current threshold. To activate IMON diagnostic function, the EN_IMON I²C bit has to be set

to “1” in the data 4 register. As soon as the IMON function is active by EN_IMON=1, V

OUT

rises 21 V (typ.) on the VSEL bit setting. This operation is applied to be sure that the

LNBH25S output has the higher voltage in the LNB bus. Do not use this function in an

application environment where 21 V voltage level is not supported by other peripherals

connected to the LNB bus.

2.15

PDO (overcurrent detection on output pull-down stage)

When an overcurrent occurs on the pull-down output stage due to an external voltage

source greater than the LNBH25S nominal VOUT and for a time longer than ISINK_TIME-OUT (10

ms typ.), PDO I²C bit is set to “1”. This may happen due to an external voltage source on

the LNB output (VOUT pin).

For current threshold and deglitch time details, see Table 13: "Electrical characteristics".

2.16

Power-on I²C interface reset and undervoltage lockout

The I²C interface, built into the LNBH25S, is automatically reset at power-on. As long as

the VCC is below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does

not respond to any I²C command and all data register bits are initialized to zero, therefore

the power blocks are disabled. Once VCC rises above 4.8 V typ. the I²C interface becomes

operative and data registers can be configured by the main microprocessor.

2.17

PNG (input voltage minimum detection)

When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum

thresholds, the PNG I²C bit is set to “1” and the FLT pin is set low. See Table 13: "Electrical

characteristics" for threshold details.

2.18

ISW (inductor switching current limit)

In order to allow low saturation current inductors to be used, the maximum DC-DC inductor

switching current limit threshold can be set by one I²C bit (ISW). Two values are available:

2.5 A typ. (with ISW = 1) and 4 A typ. (with ISW = 0).

2.19

COMP (boost capacitors and inductor)

The DC-DC converter compensation loop can be optimized to properly work with both

ceramic and electrolytic capacitors (VUP pin). For this purpose, one I²C bit in the data 4

set to “1” or “0” as follows:



COMP = 0 for electrolytic capacitors



COMP = 1 for ceramic capacitors

For recommended DC-DC capacitor and inductor values see Section 5: "Typical

application circuits" and the BOM in and Table 6: "DiSEqC 2.x bill of material".

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