RHFL6000A datasheet(16/31 Pages) STMICROELECTRONICS

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Additional guidelines for SET mitigation

RHFL6000A

16/31

DocID028379 Rev 2

Additional guidelines for SET mitigation

This section provides detailed design guidelines necessary to obtain the required

performance against SET. In this respect, we can identify two main areas for intervention:

ground connection and external components selection.

7.1

Ground connections

To achieve the best performance in terms of output voltage accuracy, noise immunity and

robustness against single event effects, it is recommended to implement a proper PCB

layout by following the suggestions described below.

According to qualitative simulations of single events, some very short SET (i.e., a duration

in the 100 ns range) are strongly dependent on the stray inductances versus GND. The

best solution to reduce the parasitic inductance is the adoption of a GND plane (with

separate power and sense paths where possible). By minimizing the stray GND

impedance, this approach is of great assistance in controlling the amplitude of the SET

events near the load.

If this solution is not applicable, we suggest using a star-bus topology, where the PCB

reference GND connection is close to the GND pin of the regulator.

To achieve a good GND sense, it is necessary to comply with the following rules:



connect the regulator GND pin and load GND node both to the sense and power GND

traces on the PCB using vias to minimize the path;



an array of multiple via structures works better than a single large one;



for GND connectors/plugs: use separate plugs for power supply and testing probes;



connect input/output capacitors GND terminals to GND sense on the PCB.

7.2

Capacitor selection

With reference to Figure 4: "Heavy Ion test configuration", a combination of capacitors must

be present on the input and output ports. For the INPUT terminals, this may consist of a

100 µF bulk capacitor (CIN1) in parallel with a polyester 100 nF one (CIN2) used for

decoupling purposes.

For each of the two OUTPUT connections (pins 1, 2 and 6, 7) we suggest using a

combination of a 47µF bulk capacitor (COUT1, COUT2,) in parallel with a polyester 100 nF one

(COUT4, COUT5) for decoupling purposes.

Regarding parts selection, for the 100 nF elements we suggest low-ESL and low ESR

capacitors.

Concerning the selection of the three bulk capacitors, we suggest:



using tantalum SMD;



selecting size and ESL as small as possible;



placing capacitors as close as possible to the input/output terminals;



using an array of capacitors in parallel, where possible. This works better than a single

capacitor against the short events.

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