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RHFL6000A Datasheet(PDF) 19 Page - STMicroelectronics

Part # RHFL6000A
Description  2 A rad-hard adjustable positive voltage regulator
PDF  31 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

RHFL6000A Datasheet(HTML) 19 Page - STMicroelectronics

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RHFL6000A
Application information
DocID028379 Rev 2
19/31
9
Application information
To adjust the output voltage, the R2 resistor must be connected between the VO and ADJ
pins. The R1 resistor must be connected between ADJ and ground. Resistor values can be
derived from the following formula:
where
The minimum output voltage is therefore VADJ and minimum input voltage is 2.5 V.
The RHFL6000A operates correctly when the VI - VO voltage difference is slightly above
the power element saturation voltage (Vd, dropout voltage).
A minimum load current of 0.5 mA must be set to ensure proper regulation under no-load
condition. It is advisable to make this current flow into the resistor divider.
For this reason, we suggest selecting an R1 value not higher than 10 k Ω.
The RHFL6000 flat16 package offers multiple input and output pins.
All of the available VI pins should always be externally interconnected. The same must be
applied to all the available VO pins, otherwise the stability and reliability of the device
cannot be guaranteed.
The inhibit function switches off the output current very quickly. According to Lenz’s Law,
external circuitry reacts with LdI/dt terms which can be of high amplitude in case of serial
inductive elements or large stray PCB inductance. Large transient voltage would develop
on both device terminals. It is advisable to protect the device output with Schottky diodes to
prevent negative voltage excursions. A14 V Zener diode could protect the device input.
The input and output capacitors must be connected as close as possible to the device
terminals.
Since the RHFL6000A voltage regulator is manufactured with very high speed bipolar
technology (6 GHz fT transistors), the PCB layout must be designed with exceptional care,
with very low inductance and low mutually coupling lines. Otherwise, high frequency
parasitic signals may be picked up by the device resulting in system self-oscillation.
On the other hand, the benefit of this technology is SVR performance extended to high
frequencies.
VO = VADJ (R1+ R2) / R1
ADJ = 1.248 V typ.
V



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