CS8900A datasheet(73/128 Pages) CIRRUS

73 / 128 page

DS271PP3

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATA SHEET

4.7 Receive and Transmit Frame Locations

The Receive and Transmit Frame PacketPage loca-

tions are used to transfer Ethernet frames to and

from the host. The host sequentially writes to and

reads from these locations, and internal buffer

memory is dynamically allocated between transmit

and receive as needed. One receive frame and one

transmit frame are accessible at a time.

4.7.1 Receive PacketPage Locations

In IO mode, the receive status/length/frame loca-

tions are read through repetitive reads from one IO

port at the IO base address. See Section 4.10 on

page 76.

In memory mode, the receive status/length/frame

locations are read using memory reads of a block of

memory starting at memory base address + 0400h.

Typically the memory locations are read sequen-

tially using repetitive Move instructions (REP

MOVS). See Section 4.9 on page 74.

Random access is not needed. However, the first

118 bytes of the receive frame can be accessed ran-

domly if word reads, on even word boundaries, are

used. Beyond 118 bytes, the memory reads must be

sequential. Byte reads, or reads on odd-word

boundaries, can be performed only in sequential

read mode. See Section 4.8 on page 73.

The RxStatus word reports the status of the current

received frame. RxEvent register 4 (PacketPage

base + 0124h) has the same contents as the RxSta-

tus register, except RxEvent is cleared when Rx-

Event is read.

The RxLength (receive length) word is the length,

in bytes, of the data to be transferred to the host

across the ISA bus. The register describes the

length from the start of Destination Address to the

end of CRC, assuming that CRC has been selected

(via Register 3 RxCFG, bit BufferCRC). If CRC

has not been selected, then the length does not in-

clude the CRC, and the CRC is not present in the

receive buffer.

After the RxLength has been read, the receive

frame can be read. When some portion of the frame

is read, the entire frame should be read before read-

ing the RxEvent register either directly or through

the ISQ register. Reading the RxEvent register sig-

nals to the CS8900A that the host is finished with

the current frame, and wants to start processing the

next frame. In this case, the current frame will no

longer be accessible to the host. The current frame

will also become inaccessible if a Skip command is

issued, or if the entire frame has been read. See

Section 5.2 on page 79.

4.7.2 Transmit Locations

The host can write frames into the CS8900A buffer

using Memory writes using REP MOVS to the Tx-

Frame location. See Section 5.7 on page 99.

4.8 Eight and Sixteen Bit Transfers

A data transfer to or from the CS8900A can be

done in either I/O or Memory space, and can be ei-

ther 16 bits wide (word transfers) or 8 bits wide

(byte transfers). Because the CS8900A’s internal

architecture is based on a 16-bit data bus, word

transfers are the most efficient.

To transfer transmit frames to the CS8900A and re-

ceive frames from the CS8900A, the host may mix

word and byte transfers, provided it follows three

rules:

1) The primary method used to access CS8900A

memory is word access.

2) Word accesses to the CS8900A’s internal

memory are kept on even-byte boundaries.

3) When switching from byte accesses to word ac-

cesses, a byte access to an even byte address

must be followed by a byte access to an odd-

byte address before the host may execute a

word access (this will realign the word transfers

to even-byte boundaries). On the other hand, a

byte access to an odd-byte address may be fol-

lowed by a word access.

CS8900A Datasheet(PDF) 73 Page - Cirrus Logic

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