CS8900A datasheet(49/128 Pages) CIRRUS

49 / 128 page

DS271PP3

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATA SHEET

operations. It is possible to set either, neither, or

both bits. The four corresponding pairs of bits are:

If one of the above Interrupt Enable bits is set and

the corresponding Accept bit is clear, the CS8900A

generates an interrupt when the associated receive

event occurs, but then does not accept the receive

frame (the length of the receive frame is set to ze-

ro).

The other five Accept bits in RxCTL are used for

destination address filtering (see Section 5.3 on

page 87). The Accept mechanism is explained in

more detail in Section 5.2 on page 79.

4.4.4 Status and Control Register Summary

The table on the following page (Table 15) pro-

vides a summary of the Status and Control regis-

ters. Section 4.4.4 on page 49 gives a detailed

description of each Status and Control register.

Interrupt Enable Bit

(register name)

Event Bit or Counter

(register name)

ExtradataiE (RxCFG)

Extradata (RxEvent)

RuntiE (RxCFG)

Runt (RxEvent)

CRCerroriE (RxCFG)

CRCerror (RxEvent)

RxOKiE (RxCFG)

RxOK (RxEvent)

16colliE (TxCFG)

16coll (TxEvent)

AnycolliE (TxCFG)

“Number-of Tx-collisions”

counter is incremented

(TxEvent)

JabberiE (TxCFG)

Jabber (TxEvent)

Out-of-windowiE (TxCFG) Out-of-window (TxEvent)

TxOKiE (TxCFG)

TxOK (TXEvent)

SQEerroriE (TxCFG)

SQEerror (TxEvent)

Loss-of-CRSiE (TxCFG)

Loss-of-CRS (TxEvent)

MissOvfloiE (BufCFG)

RxMISS counter over-

flows past 1FFh

TxColOvfloiE (BufCFG)

TxCOL counter overflows

past 1FFh

RxDestiE (BufCFG)

RxDest (BufEvent)

Rx128iE (BufCFG)

Rx128 (BufEvent)

RxMissiE (BufCFG)

RxMISS (BufEvent)

TxUnderruniE (BufCFG)

TxUnderrun (BufEvent)

Rdy4TxiE (BufCFG)

Rdy4Tx (BufEvent)

RxDMAiE (BufCFG)

RxDMAFrame (BufEvent)

Table 14. Interrupt Enable Bits and Events

IE Bit in RxCFG

A Bit in RxCTL

ExtradataiE

ExtradataA

RuntiE

RuntA

CRCerroriE

CRCerrorA

RxOKiE

RxOKA

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