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CY7C64013
CY7C64113
Document #: 38-08001 Rev. **
Page 27 of 48
just before the RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI
instruction is executed.
The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exists the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).
16.1
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed in Table 16-1. The lowest-numbered interrupt (USB Bus Reset
interrupt) has the highest priority, and the highest-numbered interrupt (I2C interrupt) has the lowest priority. Although Reset is not
an interrupt, the first instruction executed after a reset is at PROM address 0x0000h—which corresponds to the first entry in the
Interrupt Vector Table. Because the JMP instruction is 2 bytes long, the interrupt vectors occupy 2 bytes.
Figure 16-3. Interrupt Controller Functional Diagram
CLR
Global
Interrupt
Interrupt
Acknowledge
IRQout
USB Reset Clear
Interrupt
Interrupt
Priority
Encoder
Enable [0]
D
Q
1
Enable
Bit
CLR
USB Reset IRQ
128-
µs CLR
128-
µs IRQ
1-ms CLR
1-ms IRQ
AddA EP0 IRQ
AddA EP0 CLR
I2C IRQ
Vector
Enable [6]
CLK
CLR
D
Q
CLK
1
I2C CLR
Int
I2C
Int
USB
AddA EP1 IRQ
AddA EP1 CLR
IRQ Sense
IRQ
Controlled by DI, EI, and
RETI Instructions
DAC IRQ
DAC CLR
To CPU
CPU
Reset
GPIO IRQ
GPIO CLR
AddA EP2 IRQ
AddA EP2 CLR
AddA EP3 IRQ
AddA EP3 CLR
AddA EP4 IRQ
AddA EP4 CLR
(Reg 0x20)
(Reg 0x20)
CLR
Enable [2]
D
Q
1
CLK
Int
AddA
ENP2
(Reg 0x21)
Int Enable
Sense
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