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DP83907 Datasheet(PDF) 64 Page - National Semiconductor (TI) |
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DP83907 Datasheet(HTML) 64 Page - National Semiconductor (TI) |
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64 / 70 page  Preliminary Switching Design Guidelines (Continued) ISA SLAVE ACCESSES (Continued) Symbol Description 8-Bit Transfers 16-Bit Transfers Units Min Max Min Max T2 AEN Valid before Command Strobe Active 60 60 ns T3a SA0–9 Valid before IORD IOWR Asserted 40 20 ns T3b SA0–19 Valid before SMRD SMWR Asserted 32 ns T4 SMRD IORD Asserted to SD0–15 Driven (Notes 3 14) 0 0 ns T5a SA0–9 Valid before IO16 Valid (Notes 1 9) 60 ns T5c SA0–9 Valid and IORD IOWR 50 ns Active before IO16 Valid (Notes 1 10) T6a IORD IOWR Asserted to CHRDY Negated (Notes 2 5) 100 50 ns T6b SMRD SMWR Asserted to CHRDY Negated (Note 2) 100 ns T7 SMRD SMWR IORD IOWR 20 20 ns Negated before SA0–9 Invalid T9 SMRD IORD Negated to SD0–15 Read Data Invalid 00 ns (notes 3 14) T10 SMRD IORD negated to SD0–15 Floating (Note 3) 45 45 ns T11 D0–15 Write Data Valid to IOWR SMWR Negated (Note 3) 60 40 ns T12 SMWR IOWR Negated to SD0–15 Write Data Invalid (Note 3) 20 20 ns T13 SMRD SMWR IORD IOWR Active Width (Note 8) 300 140 ns T14a IORD IOWR Inactive Width 85 85 ns T14b SMRD SMWR Inactive Width 150 150 ns T17 CHRDY Asserted to SD0–15 Read 60 60 ns Data Valid (Notes 2 3 6) T18 SMRD SMWR IORD IOWR Negated before AEN Invalid 25 25 ns T20 SMRD IORD Asserted to SD0–15 Read Data Valid (Notes 3 and 7) 150 90 ns T24 Read Data Valid on MSD0–7 to Valid on SD0–7 70 ns T25 MSRD Deasserted to MSD0–7 Read Data Invalid (Note 3) 0 ns T26 Write Data Valid on SD0–7 to Valid on MSD0–7 90 ns 64 |
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