4

SN74LVTH16373-EP

SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016

www.ti.com

Product Folder Links: SN74LVTH16373-EP

Submit Documentation Feedback

Copyright © 2003–2016, Texas Instruments Incorporated

(1)

"n" denotes numbering (1 to 8) for data input and output pins.

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

37, 38, 49, 41, 43, 44, 46, 47

I

Data input pins

1LE

48

I

Latch enable pin to control 1Qn output states

1OE

1

I

Active low enable pin for 1Qn pins

2, 3, 5, 6, 8, 9, 11, 12

O

Output pins

26, 27, 29, 30, 32, 33, 35, 36

I

Data input pins

2LE

25

I

Latch enable pin to control 2Qn output states

13, 14, 16, 17, 19, 20, 22, 23

O

Output pins

2OE

24

I

Active low enable pin for 2Qn pins

GND

4, 10, 15, 21, 28, 34, 39, 45

—

Ground

VCC

7, 18, 31, 42

I

Power supply input for internal circuits

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3)

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Supply voltage

–0.5

4.6

V

–0.5

7

V

–0.5

7

V

–0.5

V

Current into any output in the low state

128

mA

64

mA

–50

mA

–50

mA

Storage temperature

–65

150

°C

(1)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge

Human body model (HBM), per A114-A

±4000

V

±3000

V

Machine model (MM), per A115-A

200

V