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CLVTH16373MGQLREP Datasheet(PDF) 1 Page - Texas Instruments |
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CLVTH16373MGQLREP Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 24 page ![]() 1OE 1LE 1D1 To Seven Other Channels 1Q1 1 48 47 2 C1 1D Product Folder Sample & Buy Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVTH16373-EP SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016 SN74LVTH16373-EP 3.3-V ABT 16-Bit Transparent D-Type Latch With Tri-State Outputs 1 1 Features 1 • Controlled Baseline – One Assembly/Test Site, One Fabrication Site • Enhanced Diminishing Manufacturing Sources (DMS) Support • Enhanced Product-Change Notification • Qualification Pedigree (1) • Member of the Texas Instruments Widebus™ Family • State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static- Power Dissipation • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) • Supports Unregulated Battery Operation Down to 2.7 V • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C • Ioff and Power-Up Tri-State Support Hot Insertion • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • Distributed VCC and GND Pins Minimize High- Speed Switching Noise • Flow-Through Architecture Optimizes PCB Layout • Latch-Up Performance Exceeds 500 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 4000-V Human Body Model (A114-A) – 200-V Machine Model (A115-A) 2 Applications • Data Buffer • Bus Driver • Display Driver 3 Description The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch- enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. Device Information(2) PART NUMBER PACKAGE BODY SIZE (NOM) SN74LVTH16373-EP TSSOP (48) 12.50 mm × 6.10 mm SSOP (48) 15.88 mm × 7.49 mm BGA MICROSTAR JUNIOR (56) 4.50 mm × 7.00 mm (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. (2) For all available packages, see the orderable addendum at the end of the data sheet. SN74LVTH16373-EP Single Channel Block Diagram |
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