DP8420V datasheet(43/60 Pages) NSC

43 / 60 page

130 AC Timing Parameters

Two speed selections are given the DP8420V21V22V-33

and the DP84T22-25 The differences between the two

parts are the maximum operating frequencies of the input

CLKs and the maximum delay specifications Low frequency

applications may use the ‘‘-33’’ part to gain improved timing

The AC timing parameters are grouped into sectional num-

bers as shown below These numbers also refer to the tim-

ing diagrams

1 – 36

Common parameters to all modes of operation

50 – 56

Difference parameters used to calculate

RAS low time

RAS precharge time

CAS high time and

CAS low time

100 – 121 Common dual access parameters used for Port

B accesses and inputs and outputs used only in

dual accessing

200 – 212 Refresh parameters

300 – 315 Mode 0 access parameters used in both single

and dual access applications

400 – 416 Mode 1 access parameters used in both single

and dual access applications

450 – 455 Special Mode 1 access parameters which super-

sede the 400 – 416 parameters when dual ac-

cessing

500 – 506 Programming parameters

Unless otherwise stated VCC e 50V g10% 0 k TA k

70 C the output load capacitance is typical for 4 banks of

18 DRAMs per bank including trace capacitance (see Note

Two different loads are specified

CL e 50 pF loads on all outputs except

CL e 150 pF loads on Q0–8 9 10 and WE or

CH e 50 pF loads on all outputs except

CH e 125 pF loads on RAS0–3 and CAS0–3 and

CH e 380 pF loads on Q0–8 9 10 and WE

TLF11109 – 63

FIGURE 36 Clock DELCLK Timing

DP8420V Datasheet(PDF) 43 Page - National Semiconductor (TI)