DP8420V datasheet(22/60 Pages) NSC

22 / 60 page

50 Refresh Options (Continued)

512 Externally ControlledBurst Refresh

To use externally controlledburst refresh the user must

disable the automatic internally controlled refreshes by as-

serting the input DISRFSH The user is responsible for gen-

erating the refresh request by asserting the input RFSH

Pulsing RFSH low sets an internal latch that is used to

produce the internal refresh request The refresh cycle will

take place on the next positive edge of CLK as shown in

Figure 14a If an access to DRAM is in progress or pre-

charge time for the last access has not been met the re-

fresh will be delayed Since pulsing RFSH low sets a latch

the user does not have to keep RFSH low until the refresh

starts When the last refresh RAS negates the internal re-

fresh request latch is cleared

TLF11109 – 22

FIGURE 14a Single External Refreshes (2 Periods of RAS Low during Refresh Programmed)

By keeping RFSH asserted past the positive edge of CLK

which ends the refresh cycle as shown in

Figure 14b the

user will perform another refresh cycle Using this tech-

nique the user can perform a burst refresh consisting of any

number of refresh cycles Each refresh cycle during a burst

refresh will meet the refresh RAS low time and the RAS

precharge time (programming bits R0 – 1)

If the user desires to burst refresh the entire DRAM (all row

addresses) he could generate an end of count signal (burst

refresh finished) by looking at one of the DP8420V21V

22V DP84T22 high address outputs (Q7 Q8 Q9 or Q10)

and the RFIP output The Qn outputs function as a decode

of how many row addresses have been refreshed (Q7 e

128 refreshes Q8 e 256 refreshes Q9 e 512 refreshes

Q10 e 1024 refreshes)

TLF11109 – 23

FIGURE 14b External Burst Refresh (2 Periods of RAS Precharge

2 Periods of Refresh RAS Low during Refresh Programmed)

DP8420V Datasheet(PDF) 22 Page - National Semiconductor (TI)