DP8420V datasheet(49/60 Pages) NSC

49 / 60 page

130 AC Timing Parameters (Continued)

Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified

CL e 50 pF loads on all outputs except

CL e 150 pF loads on Q0–8 9 10 and WE or

CH e 50 pF loads on all outputs except

CH e 125 pF loads on RAS0–3 and CAS0–3 and

CH e 380 pF loads on Q0–8 9 10 and WE

Refresh Parameter

DP8420V21V22V and DP84T22V

Number

Symbol

Description

Min

Max

Min

Max

200

tSRFCK

RFSH Asserted Setup to CLK High

201

tSDRFCK

DISRFSH Asserted Setup to CLK High

202

tSXRFCK

EXTENDRF Setup to CLK High

204

tPCKRFL

CLK High to RFIP Asserted

205

tPARQRF

AREQ Negated to RFIP Asserted

206

tPCKRFH

CLK High to RFIP Negated

207

tPCKRFRASH

CLK High to Refresh RAS Negated

208

tPCKRFRASL

CLK High to Refresh RAS Asserted

209a

tPCKCL0

CLK High to CAS Asserted

during Error Scrubbing

(tRAH e 15 ns tASC e 0 ns)

209b

tPCKCL1

CLK High to CAS Asserted

during Error Scrubbing

(tRAH e 15 ns tASC e 10 ns)

209c

tPCKCL2

CLK High to CAS Asserted

during Error Scrubbing

(tRAH e 25 ns tASC e 0 ns)

209d

tPCKCL3

CLK High to CAS Asserted

during Error Scrubbing

(tRAH e 25 ns tASC e 10 ns)

210

tWRFSH

RFSH Pulse Width

211

tPCKRQL

CLK High to RFRQ Asserted

212

tPCKRQH

CLK High to RFRQ Negated

TLF11109 – 66

FIGURE 39 200 Refresh Timing

DP8420V Datasheet(PDF) 49 Page - National Semiconductor (TI)

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