DP8420V datasheet(45/60 Pages) NSC

45 / 60 page

130 AC Timing Parameters (Continued)

Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified

CL e 50 pF loads on all outputs except

CL e 150 pF loads on Q0–8 9 10 and WE or

CH e 50 pF loads on all outputs except

CH e 125 pF loads on RAS0–3 and CAS0–3 and

CH e 380 pF loads on Q0–8 9 10 and WE

Common Parameter

DP8420V21V22V and DP84T22V

Number

Symbol

Description

Min

Max

Min

Max

tPEDL

ECAS Asserted to DTACK

Asserted during a Burst Access

(Programmed as DTACK0)

tPEDH

ECAS Negated to DTACK

Negated during a Burst Access

tSWCK

WAITIN Asserted Setup to CLK

tPWINWEH

WIN Asserted to WE Asserted

tPWINWEL

WIN Negated to WE Negated

tPAQ

Row Column Address Valid to

Q0 – 8 9 10 Valid

tPCINCQ

COLINC Asserted to Q0 – 8 9 10

Incremented

tSCINEN

COLINC Asserted Setup to ECAS

Asserted to Ensure tASC e 0ns

29a

tSARQCK1

AREQ AREQB Negated Setup to CLK

High with 1 Period of Precharge

29b

tSARQCK2

AREQ AREQB Negated Setup to CLK High

with l1 Period of Precharge Programmed

tPAREQDH

AREQ Negated to DTACK Negated

tPCKCAS

CLK High to CAS Asserted

when Delayed by WIN

tSCADEN

Column Address Setup to ECAS

Asserted to Guarantee tASC e 0

tWCINC

COLINC Pulse Width

34a

tPCKCL0

CLK High to CAS Asserted following

Precharge (tRAH e 15 ns tASC e 0 ns)

34b

tPCKCL1

CLK High to CAS Asserted following

Precharge (tRAH e 15 ns tASC e 10 ns)

34c

tPCKCL2

CLK High to CAS Asserted following

Precharge (tRAH e 25 ns tASC e 0 ns)

34d

tPCKCL3

CLK High to CAS Asserted following

Precharge (tRAH e 25 ns tASC e 10 ns)

tCAH

Column Address Hold Time

(Interleave Mode Only)

tPCQR

CAS Asserted to Row Address

Valid (Interleave Mode Only)

DP8420V Datasheet(PDF) 45 Page - National Semiconductor (TI)

DP8420V Datasheet(HTML) 45 Page - National Semiconductor (TI)

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