DP8422V datasheet(36/60 Pages) NSC

36 / 60 page

80 Test Mode

Staggered refresh in combination with the error scrubbing

mode places the DP8420V21V22V DP84T22 in test

mode In this mode the 24-bit refresh counter is divided into

a 13-bit and 11-bit counter During refreshes both counters

are incremented to reduce test time

90 DRAM Critical Timing

Parameters

The two critical timing parameters shown in

Figure 31 that

must be met when controlling the access timing to a DRAM

are the row address hold time tRAH and the column ad-

dress setup time

tASC Since the DP8420V21V22V

DP84T22 contain a precise internal delay line the values of

these parameters can be selected at programming time

These values will also increase and decrease if DELCLK

varies from 2 MHz

91 PROGRAMMABLE VALUES OF tRAH AND tASC

The DP8420V21V22V DP84T22 allow the values of tRAH

and tASC to be selected at programming time For each pa-

rameter two choices can be selected tRAH the row ad-

dress hold time is measured from RAS asserted to the row

address starting to change to the column address The two

choices for tRAH are 15 ns and 25 ns programmable

through address bit C8

tASC the column address setup time is measured from the

column address valid to CAS asserted The two choices for

tASC are 0 ns and 10 ns programmable through address bit

92 CALCULATION OF tRAH AND tASC

There are two clock inputs to the DP8420V21V22V

DP84T22 These two clocks DELCLK and CLK can either

be tied together to the same clock or be tied to different

clocks running asynchronously at different frequencies

The clock input DELCLK controls the internal delay line

and refresh request clock DELCLK should be a multiple of

2 MHz If DELCLK is not a multiple of 2 MHz tRAH and tASC

will change The new values of tRAH and tASC can be calcu-

lated by the following formulas

If tRAH was programmed to equal 15 ns then tRAH e

15 (((DELCLK Divisor)

2 MHz(DELCLK Frequency))b1)

15 ns

If tRAH was programmed to equal 25 ns then tRAH e

25 (((DELCLK Divisor)

2 MHz(DELCLK Frequency))b1)

25 ns

If tASC was programmed to equal 0 ns then tASC e

125 ((DELCLK Divisor) 2 MHz(DELCLK Frequency)) b

125 ns

If tASC was programmed to equal 10 ns then tASC e

225 ((DELCLK Divisor) 2 MHz(DELCLK Frequency)) b

225 ns

Since the values of tRAH and tASC are increased or de-

creased the time to CAS asserted will also increase or de-

crease These parameters can be adjusted by the following

formula

Delay to CAS e Actual Spec a Actual tRAH b

Programmed tRAH a Actual tASC b Programmed tASC

TLF11109 – 50

FIGURE 31 tRAH and tASC

DP8422V Datasheet(PDF) 36 Page - National Semiconductor (TI)

DP8422V Datasheet(HTML) 36 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL