| Electronic Components Datasheet Search |
|
DP8422V Datasheet(PDF) 41 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
DP8422V Datasheet(HTML) 41 Page - National Semiconductor (TI) |
|
41 / 60 page ![]() 100 Dual Accessing (DP8422V DP84T22) (Continued) 1032 LOCK Input When the LOCK input is asserted the currently granted port can ‘‘lock out’’ the other port through the insertion of wait states to that port’s access cycle LOCK does not disable refreshes it only keeps GRANTB in the same state even if the other port requests an access as shown in Figure 35 LOCK can be used by either port TLF11109 – 61 FIGURE 35 LOCK Function 104 TRI-STATE OUTPUTS (DP84T22V Only) This version is a metal option on the DP8420V21V22V-33 DRAM controllers It comes in a 84-pin PLCC and imple- ments TRI-STATE output capabilities It has only one extra pin OE When OE is asserted the output buffers are enabled allowing the DRAM controller to interface to the DRAM ar- ray If OE is negated the output buffers are at TRI-STATE (high- Z) making the board level circuit testing easier The time penalty for the TRI-STATE option has been minimized mak- ing this option attractive to high performance designs This part is functionally compatible to the DP8422A-20 -25 TRI-STATE Output Drivers TLF11109 – 62 41 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |