TMS320C6472ECTZ datasheet(152/269 Pages) TI1

152 / 269 page

TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

www.ti.com

7.8.2

PLL1 Controller Peripheral Register Descriptions

The memory map of the PLL1 controller is shown in Table 7-20. Note that only registers documented here

are accessible on the C6472. Other addresses in the PLL1 controller memory map are reserved and

should not be modified.

Table 7-20. PLL1 Controller Registers

HEX ADDRESS RANGE

ACRONYM

029A 0000

PID

Peripheral Identification Register [value: 0001 0802h]

029A 0004 - 029A 00E0

Reserved

029A 00E4

RSTYPE

Reset Type Status Register

029A 00E8 - 029A 00FC

Reserved

029A 0100

PLLCTL

PLL Control Register

029A 0104 - 029A 010C

Reserved

029A 0110

PLLM

PLL Multiplier Control Register

029A 0114 - 029A 0134

Reserved

029A 0138

PLLCMD

PLL Controller Command Register

029A 013C

PLLSTAT

PLL Controller Status Register

029A 0140

Reserved

029A 0144

DCHANGE

PLLDIV Ratio Change Status Register

029A 0148 - 029A 01FC

Reserved

029A 0150

SYSTAT

SYSCLK Status Register

029A 0154 - 029A 0174

Reserved

029A 0178

PLLDIV10

PLL Controller Divider 10 Register for SYSCLK10

029A 017C - 029A 03FC

Reserved

152

C64x+ Peripheral Information and Electrical Specifications

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