TMS320C6472ECTZ datasheet(237/269 Pages) TI1

237 / 269 page

TMS320C6472

www.ti.com

SPRS612G

– JUNE 2009 – REVISED JULY 2011

7.16 Timers

The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send

synchronization events to the EDMA. The localized timers (Timer 0 - Timer 5) can also be used as

watchdog timers.

7.16.1 Timer Device-Specific Information

The C6472 device has six localized timers (Timer 0 - Timer 5) and six shared timers (Timer 6 - Timer 11).

Each of the localized timers can be configured as a general-purpose timer or a watchdog timer. Each of

the shared timers is a general-purpose timer. When configured as a general-purpose timer, each timer

can be programmed as a 64-bit timer or as two separate 32-bit timers. The localized timers are clocked

with an internal clock with a CPU/6 frequency. The shared timers can also be clocked with the same

internal clock frequency or with an external signal provided on TIMI0 or TIMI1.

Each timer is made up of two 32-bit counters: a high counter and a low counter. The TIMI0 pin is

connected to the low counter of each of the shared timers and the TIMI1 pin is connected to the high

counter of each of the shared timers. The output of one of the shared timers, either the high counter or the

low counter, can be selected to be output on the timer output pin (TIMO2).

When Timer 0 - Timer 5 are configured as watchdog timers, each core should maintain its own watchdog.

Each core should also configure the corresponding RSTMUX0-5 register (see Section 3.8.2) to define the

action that will be taken if a watchdog timeout occurs. In addition to the internally defined actions, a

watchdog timeout results in the assertion of the WDOUT pin. WDOUT is a logically-combined signal from

the six individual watchdog timers. A host can determine which of the six cores experienced the watchdog

timeout by reading the RSTMUX registers or having the contents of those registers reported by one of the

cores.

7.16.2 Timer Peripheral Register Descriptions

Table 7-127. Timer 0 Registers

HEX ADDRESS RANGE

ACRONYM

025E 0000

Reserved

025E 0004

EMUMGT_CLKSPD0

Timer 0 Emulation Management/Clock Speed Register

025E 0008

Reserved

025E 000C

Reserved

025E 0010

CNTLO0

Timer 0 Counter Register Low

025E 0014

CNTHI0

Timer 0 Counter Register High

025E 0018

PRDLO0

Timer 0 Period Register Low

025E 001C

PRDHI0

Timer 0 Period Register High

025E 0020

TCR0

Timer 0 Control Register

025E 0024

TGCR0

Timer 0 Global Control Register

025E 0028

WDTCR0

Timer 0 Watchdog Timer Control Register

025E 002C - 025E FFFC

Reserved

C64x+ Peripheral Information and Electrical Specifications

237

Submit Documentation Feedback

Product Folder Link(s) :TMS320C6472

TMS320C6472ECTZ Datasheet(PDF) 237 Page - Texas Instruments

TMS320C6472ECTZ Datasheet(HTML) 237 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL