CS8952T datasheet(28/86 Pages) CIRRUS

28 / 86 page

DS206TPP2

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

erate without the preamble through bit 9 of the PCS

Sub-Layer Configuration Register (address 17h).

Table 6. MII Management Interface Frame Format

The Start of Frame is indicated by a 01 bit pattern.

A read transaction is indicated by an Opcode of 10

andawrite by01.

The PHY Address is five bits, with the most signif-

icant bit sent first. If the PHY address included in

the frame is not 00000 or does not match the PHY-

AD field of the Self Status Register (address 19h),

the rest of the frame is ignored.

The register address is five bits, with the most sig-

nificant bit sent first, and indicates the CS8952T

The Turnaround time is a two bit time spacing be-

tween when the MAC drives the last register ad-

dress bit onto MDIO and the data field of a

management frame in order to avoid contention

during a read transaction. For a read transaction,

the MAC should tri-state the MDIO pin beginning

on the first bit time, and the CS8952T will begin

driving the MDIO signal to a logic ZERO during

the second bit time. During write transactions,

since the MDIO direction does not need to be re-

versed, the MAC will drive the MDIO to a logic

ONE for the first bit time and a logic ZERO for the

second.

The data field is always 16 bits in length, with the

most significant bit sent first.

Preamble

(32 bits)

Start of

Frame

(2 bits)

Opcode

(2 bits)

PHY

Address

(5 bits)

Address

(5 bits)

Turnaround

(2 bits)

Data

(16 bits)

Idle

CS8952T Datasheet(PDF) 28 Page - Cirrus Logic

CS8952T Datasheet(HTML) 28 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Datasheet Download

Link URL