3

DAC8534

SBAS254D

www.ti.com

REFERENCE INPUT

Reference Current

135

180

µA

80

120

µA

Reference Input Range

0

V

Reference Input Impedance

37

k

Ω

Input Current

±1

µA

V

IOV

0.8

V

V

IOV

0.6

V

V

IOV

2.4

V

V

IOV

2.1

V

Pin Capacitance

3pF

POWER REQUIREMENTS

AV

DD

2.7

5.5

V

IOV

DD

2.7

5.5

V

DAC Active and Excluding Load Current

10

20

µA

AI

V

0.95

1.6

mA

AI

V

0.9

1.5

mA

AI

AI

V

0.8

1

µA

AI

V

0.05

1

µA

POWER EFFICIENCY

89

%

TEMPERATURE RANGE

Specified Performance

–40

+105

°C

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

AV

DAC8534

NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested.

PIN

NAME

DESCRIPTION

Analog output voltage from DAC A.

Analog output voltage from DAC B.

Positive reference voltage input.

Power supply input, +2.7V to +5.5V.

Negative reference voltage input.

6

GND

Ground reference point for all circuitry on the part.

Analog output voltage from DAC C.

Analog output voltage from DAC D.

9

SYNC

Level-triggered control input (active LOW). This is

the frame synchronization signal for the input data.

When SYNC goes LOW, it enables the input shift

register and data is transferred in on the falling

edges of the following clocks. The DAC is updated

following the 24th clock (unless SYNC is taken

HIGH before this edge in which case the rising edge

of SYNC acts as an interrupt and the write sequence

is ignored by the DAC8534).

10

SCLK

Serial Clock Input. Data can be transferred at rates

up to 30MHz.

11

Serial Data Input. Data is clocked into the 24-bit

input shift register on each falling edge of the serial

clock input.

12

Digital Input-Output Power Supply

13

A0

Address 0 — sets device address, see Table II.

14

A1

Address 1 — sets device address, see Table II.

15

ENABLE

Active LOW, ENABLE LOW connects the SPI inter-

face to the serial port.

16

LDAC

Load DACs, rising edge triggered loads all DAC

registers.

PIN DESCRIPTIONS

PIN CONFIGURATION

Top View

TSSOP

V

V

V

AV

DD

V

GND

V

V

LDAC

ENABLE

A1

A0

IOV

DD

D

IN

SCLK

SYNC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DAC8534