DA9211 datasheet(6/74 Pages) DIALOG

6 / 74 page

DA9211 and DA9212

Datasheet

Company confidential

Data sheet

Version <3.0>

<07-Jan-2015>

CFR0011-120-00 Rev 3

6 of 74

Figures

Figure 1: DA9211 System diagram ....................................................................................................... 2

Figure 2: DA9212 System diagram ....................................................................................................... 3

Figure 4: Connection diagram ............................................................................................................... 8

Figure 5: 2-WIRE Bus Timing.............................................................................................................. 18

Figure 6: 4-WIRE Bus Timing.............................................................................................................. 19

Figure 32: Interface of DA9211/12 with DA9063 and the host processor ........................................... 28

Figure 33: Typical application of DA9211............................................................................................ 29

Figure 34: Typical application of DA9212............................................................................................ 31

Figure 3

5: Concept of control of the buck’s output voltage ................................................................. 34

Figure 36: GPIO principle of operation (example paths) ..................................................................... 38

Figure 37: Schematic of 4-WIRE and 2-WIRE Power Manager Bus .................................................. 41

Figure 38: 4-

WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’) ............. 42

Figure 39: 4-

WIRE Host Write and Read Timing (nCS_POL= ‘0’, CPOL = ‘0’, CPHA = ‘1’) .............. 42

Figure 40: 4-WIRE Ho

st Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘0’) ............. 43

Figure 41: 4-

WIRE Host Write and Read Ttiming (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’) ............ 43

Figure 42: Timing of 2-WIRE START and STOP Condition ................................................................ 45

Figure 43: 2-WIRE Byte Write (SDA Line) .......................................................................................... 46

Figure 44: Examples of 2-WIRE Byte Read (SDA Line) ..................................................................... 46

Figure 45: Examples of 2-WIRE Page Read (SDA Line) .................................................................... 46

Figure 46: 2-WIRE Page Write (SDA Line) ......................................................................................... 47

Figure 47: 2-WIRE Repeated Write (SDA Line) .................................................................................. 47

Figure 49: DA9211/12 WL-CSP package outline drawing .................................................................. 73

Tables

Table 1: Ordering information................................................................................................................ 8

Table 2: Pin description ......................................................................................................................... 9

Table 3: Pin type definition .................................................................................................................. 10

Table 4: Absolute maximum ratings (Note 1) ...................................................................................... 11

Table 5: Recommended operating conditions (Note 1)....................................................................... 11

Table 6: Buck Converters Characteristics ........................................................................................... 12

Table 7: IC Performance and Supervision .......................................................................................... 15

Table 8: Digital I/O Characteristics ...................................................................................................... 16

Table 9: 2-WIRE Control Bus Characteristics ..................................................................................... 17

Table 10: 4-WIRE Control Bus Characteristics ................................................................................... 19

Table 11: Graphs of Typical Characteristics ....................................................................................... 20

Table 12: Selection of the buck current limit from the coil parameters ............................................... 35

Table 13: 4-WIRE Clock Configurations.............................................................................................. 41

Table 14: 4-WIRE Interface Summary ................................................................................................ 44

Table 15: Over-temperature thresholds .............................................................................................. 48

Table 16: Register map ....................................................................................................................... 49

Table 17: Recommended capacitor types........................................................................................... 71

Table 18: Recommended inductor types............................................................................................. 72

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