ADV7181BBCPZ datasheet(45/96 Pages) AD

45 / 96 page

ADV7181B

Rev. 0 | Page 45 of 96

PVENDSIGN PAL VSync End Sign, Address 0xE9 [5]

Setting PVENDSIGN to 0 (default) delays the end of VSync. Set

for user manual programming.

Setting PVENDSIGN to 1 advances the end of VSync. Not

recommended for user programming.

PVEND[4:0] PAL VSync End, Address 0xE9,[4:0]

The default value of PVEND is 10100, indicating the PAL VSync

end position.

For all NTSC/PAL VSync timing controls, both the V bit in the

AV code and the VSync on the VS pin are modified.

PFTOGDELO PAL Field Toggle Delay on Odd Field,

Address 0xEA [7]

When PFTOGDELO is 0 (default), there is no delay.

Setting PFTOGDELO to 1 delays the F toggle/transition on an

odd field by a line relative to PFTOG.

PFTOGDELE PAL Field Toggle Delay on Even Field,

Address 0xEA [6]

When PFTOGDELE is 0, there is no delay.

Setting PFTOGDELE to 1 (default) delays the F

toggle/transition on an even field by a line relative to PFTOG.

PFTOGSIGN PAL Field Toggle Sign, Address 0xEA [5]

Setting PFTOGSIGN to 0 delays the Field transition. Set for

user manual programming.

Setting PFTOGSIGN to 1 (default) advances the Field

transition. Not recommended for user programming.

PFTOG PAL Field Toggle, Address 0xEA [4:0]

The default value of PFTOG is 00011, indicating the PAL Field

toggle position.

For all NTSC/PAL Field timing controls, the F bit in the AV

code and the Field signal on the FIELD/DE pin are modified.

ADVANCE TOGGLE OF

FIELD BY PTOG[4:0]

DELAY TOGGLE OF

FIELD BY PFTOG[4:0]

PFTOGSIGN

ODD FIELD?

YES

PFTOGDELE

ADDITIONAL

DELAY BY

1 LINE

PFTOGDELO

ADDITIONAL

DELAY BY

1 LINE

FIELD

TOGGLE

NOT VALID FOR USER

PROGRAMMING

Figure 29. PAL F Toggle

SYNC PROCESSING

The ADV7181B has two additional sync processing blocks that

postprocess the raw synchronization information extracted

from the digitized input video. If desired, the blocks can be

disabled via the following two I2C bits.

ENHSPLL Enable HSync Processor, Address 0x01 [6]

The HSYNC processor is designed to filter incoming HSyncs

that have been corrupted by noise, providing improved per-

formance for video signals with stable time bases but poor SNR.

Setting ENHSPLL to 0 disables the HSync processor.

Setting ENHSPLL to 1 (default) enables the HSync processor.

ENVSPROC Enable VSync Processor, Address 0x01 [3]

This block provides extra filtering of the detected VSyncs to

give improved vertical lock.

Setting ENVSPROC to 0 disables the VSync processor.

Setting ENVSPROC to 1(default) enables the VSync processor.

ADV7181BBCPZ Datasheet(PDF) 45 Page - Analog Devices

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