ADV7181BBCPZ datasheet(79/96 Pages) AD

79 / 96 page

ADV7181B

Rev. 0 | Page 79 of 96

Bits

Subaddress

Bit Description

210

Comments

Notes

HSE[10:8]. HS end allows the

positioning of the HS output within

the video line.

HS output ends HSE[10:0]

pixels after the falling edge

of HSync

Reserved

Set to 0

HSB[10:8]. HS begin allows the

positioning of the HS output within

the video line.

HS output starts HSB[10:0]

pixels after the falling edge

of HSync

0x34

Position

Control 1

Reserved

Set to 0

0x35

Position

Control 2

HSB[7:0] See above, using HSB[10:0]

and HSE[10:0], the user can program

the position and length of HS output

signal.

0x36

Position

Control 3

HSE[7:0] See above.

Using HSB and HSE

the user can

program the

position and length

of the output HSync

Invert polarity

PCLK. Sets the polarity of LLC1.

Normal polarity as per the

timing diagrams

Reserved

Set to 0

Active high

PF. Sets the FIELD polarity.

Active low

Reserved

Set to 0

Active high

PVS. Sets the VS Polarity.

Active low

Reserved

Set to 0

Active high

0x37

Polarity

PHS. Sets HS Polarity.

Active low

ADV7181BBCPZ Datasheet(PDF) 79 Page - Analog Devices

ADV7181BBCPZ Datasheet(HTML) 79 Page - Analog Devices

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