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CS5376A Datasheet(PDF) 1 Page - Cirrus Logic |
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CS5376A Datasheet(HTML) 1 Page - Cirrus Logic |
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1 / 107 page  1 Copyright © Cirrus Logic, Inc. 2004 (All Rights Reserved) http://www.cirrus.com CS5376A Low Power Multi-Channel Decimation Filter Features 1 to 4 Channel Digital Decimation Filter Multiple On-Chip FIR and IIR Coefficient Sets Programmable Coefficients for Custom Filters Synchronous Operation Selectable Output Word Rate 4000, 2000, 1000, 500, 333, 250 SPS 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS Digital Gain and Offset Corrections Test DAC Bit Stream Generator Sine Wave or Impulse Output Mode Time Break Controller, General Purpose I/O Secondary SPI Port, Boundary Scan JTAG Microcontroller or EEPROM Configuration Small Footprint 64-pin TQFP Package Low Power Consumption 9 mW per Channel at 500 SPS Flexible Power Supplies I/O Interface: 3.3 V or 5.0 V Digital Logic Core: 3.0 V, 3.3 V or 5.0 V Description The CS5376A is a multi-function digital filter utilizing a low-power signal processing architecture to achieve effi- cient filtering for up to four ∆Σ modulators. By combining the CS5376A with CS3301/02 differential amplifiers, CS5371/72 ∆Σ modulators, and the CS4373 ∆Σ test DAC a synchronous high resolution multi-channel mea- surement system can be designed quickly and easily. Digital filter coefficients for the CS5376A FIR and IIR fil- ters are included on-chip for a simple setup, or they can be programmed for custom applications. Selectable dig- ital filter decimation ratios produce output word rates from 4000 SPS to 1 SPS, resulting in measurement bandwidths ranging from 1600 Hz down to 400 mHz when using the on-chip coefficient sets. The CS5376A includes integrated peripherals to simplify system design: offset and gain corrections, a test DAC bit stream generator, a time break controller, 12 general purpose I/O pins, a secondary SPI port, and a boundary scan JTAG port. ORDERING INFORMATION CS5376A-IQ -40 to +85 oC 64-pin TQFP I SCK 1 S e ria l D a ta O u tp u t P o rt De cim a tio n an d F ilte rin g E n g in e M o d u la to r D a ta In te rfa c e T est B it S tre am C o n tro ll er C lo ck a n d S ync hron iz a tio n TB SC LK TB SD AT A SP I 1 S e rial P e rip h eral In te rface 1 JT AG In te rface T im e B re a k C o n tr o lle r SP I 2 S e rial P e rip h eral In te rface 2 GP IO G e n e ra l P u r p o s e I/ O SYN C CL K MC L K M SYNC TIM E B MIS O MO S I SSI SINT SCK 2 SO SI1 SI2 SI3 SI4 G P IO 1 1 :EECS GP IO 1 0 GP IO 9 GP IO 8 GP IO 7 GP IO 6 GP IO 5 GP IO 4 :C S 4 GP IO 3 :C S 3 GP IO 2 :C S 2 GP IO 1 :C S 1 GP IO 0 :C S 0 FEB ‘04 DS612F1 |
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