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TAS5036IPFCR Datasheet(PDF) 33 Page - Texas Instruments |
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TAS5036IPFCR Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 49 page  System Initialization 28 SLES044B—November 2002 TAS5036 4 System Initialization Reset is used during system initialization to hold the TAS5036 inactive while power (VDD), the master clock (MCLK_IN), the device control, and the data signals become stable. The recommended initialization sequence is to hold RESET low for 24 MCLK_IN cycles after VDD has reached 3 V and the other control signals (MUTE, PDN, M_S, ERR_RCVRY,, DBSPD, and CS0) are stable. MCLK VDD 3 V 24 MCLK_IN Cycles RESET Figure 4–1. RESET During System Initialization The serial data interface format is then set through the serial data interface control register using the serial control interface. At this point the TAS5036 is fully operational. However, the operation of the TAS5036 can be tailored as desired to meet specific operating requirements by adjusting the following: • Automute delay register • DC-Offset control registers • Interchannel delay registers |
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