TAS5036IPFCR datasheet(32/49 Pages) TI

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Serial Control Interface Register Definitions

SLES044B—November 2002

TAS5036

3.7

DC-Offset Control Registers (x06–x0B)

Channels 1, 2, 3, 4, 5, and 6 are mapped into (x06, x07, x08, x09, x0A, and x0B).

Table 3–8. DC-Offset Control Registers

FUNCTION

Maximum correction for positive dc offset (–1.56% FS)

No dc-offset correction

Maximum correction for negative dc offset (1.56% FS)

3.8

Interchannel Delay Registers (x0C–x11)

Channels 1, 2, 3, 4, 5, and 6 are mapped into (x0C, x0D, x0E, x0F, x10, and x11).

The first channel delay is set at 0. Each subsequent channel has a default value that is 16 DCLKs larger than

the preceding channel.

Table 3–9. Six Inter-Channel Delay Registers

FUNCTION

Minimum absolute delay, 0 DCLK cycles, default for channel 1

Default for channel 2

Default for channel 3

Default for channel 4

Default for channel 5

Default for channel 6

Maximum absolute delay, 255 DCLK cycles

3.9

ABD Delay Register (x12)

Table 3–10. ABD Delay Register

FUNCTION

Unused

Minimum ABD delay, 0 DLCK cycles

Default ABD delay, 11 DLCK cycles

Maximum ABD delay, 31 DLCK cycles

3.10 Individual Channel Mute Register (x19)

Table 3–11. Individual Channel Mute Register

FUNCTION

Unused

No channels are muted

Mute channel 1

Mute channel 2

Mute channel 3

Mute channel 4

Mute channel 5

Mute channel 6

TAS5036IPFCR Datasheet(PDF) 32 Page - Texas Instruments

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