COM20022ITQFP datasheet(20/83 Pages) SMSC

20 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

Rev. 08-18-03

Page 20

SMSC COM20022I

DATASHEET

5.1.1

Selection of 8/16-Bit Access

The interface to the internal RAM is software selectable as either 8 or 16-bit. This feature is new to the

COM20022I. The D15-D8 pins are the upper-byte data bus pins. The nIOCS16 pin is the 16-bit I/O access

enable output pin. This pin is active low for a 16-bit RAM access by the CPU (not a DMA access).

The 16-bit access mode is enabled and disabled through the W16 bit located in the Bus Control Register

at bit 7. The SWAP bit is used to swap the upper and lower data bytes in 16-bit mode, as shown in the

table below. The SWAP bit is located at bit 0 of Address Low Pointer. This location is same as the A0 bit;

when 16 bit access is enabled (W16 =1), the A0 bit becomes the SWAP bit.

DETECTED HOST I/F MODE

SWAP BIT (NOTE)

D15-D8 PINS

D7-D0 PINS

Intel 80xx Mode

(RD,WR Mode)

Odd

Even

Odd

Motorola 68xx Mode

(DIR, DS Mode)

Even

Odd

Even

Note:

The SWAP bit is undefined after a hardware reset

As shown on the table above, even address data is to/from D7-D0 pins and odd address data is to/from

D15-D8 pins when detected host interface mode is Intel 80xx mode and the SWAP bit is not set. The odd

address data is to/from the D7-D0 pins and the even address data is to/from D15-D8 pins when detected

host interface mode is Motorola 68xx mode and the SWAP bit is not set.

When disabling 16-bit access, the D15-D8 pins are always Hi-Z. The D15-D8 pins are Hi-Z when enabling

16-bit access except for internal RAM access.

W16 bit and SWAP bit influence both the CPU cycle and DMA cycle.

5.1.2

DMA Transfers To And From Internal RAM

The COM20022I supports DMA transfers to and from the internal RAM. This feature is new to the

COM20022I. The software selectable 8/16 bit interface to the RAM pertains to DMA transfers. When the

W16 bit=0, the microcontroller interface and DMA transfers are both 8-bit data transfers to/from internal

RAM. When W16=1 they are both 16-bit data transfers. An 8-bit microcontroller interface and 16-bit DMA

data transfer cannot be selected; they must be the same width data transfers to/from internal RAM.

The data swapping operation on 16-bit data transfers also pertains to both.

The DMA interface consists of several added pins. The DREQ pin is the DMA Request output pin. The

active polarity of this pin is programmable; the default is active-high. The nDACK pin is the active-low DMA

acknowledge input pin. The TC pin is the external terminal count input pin. This pin determines when the

nDACK pin is active. It’s active polarity is programmable; the default is active-high. The nREFEX pin is the

active-low refresh execution pulse input pin.

The DMA interface is controlled by the following bits. The DMAEND bit selects whether or not to mask the

interrupt upon finishing the DMA. This bit is located at bit 4 of the Mask register. The DMAEN bit is used to

disable/enable the assertion of the DMA Request (DREQ pin) after writing the Address Pointer Low

Bus Control Register: DRPOL, TCPOL and DMAMD[1,0]. The DRQPOL bit sets the active polarity of the

DREQ pin; the TCPOL bit sets the active polarity of the TC pin; the DMAMD[1,0] bits select the data

transfer mode of the DMA.

The ITCEN/RTRG bit has one of two functions, depending on the DMA transfer mode selected. ITCEN is

the Internal Terminal Counter Enable. It is used to select whether the DMA is terminated by external TC

COM20022ITQFP Datasheet(PDF) 20 Page - SMSC Corporation

COM20022ITQFP Datasheet(HTML) 20 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Datasheet Download

Link URL