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COM20022ITQFP Datasheet(PDF) 29 Page - SMSC Corporation |
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COM20022ITQFP Datasheet(HTML) 29 Page - SMSC Corporation |
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29 / 83 page ![]() 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet SMSC COM20022I Page 29 Rev. 08-18-03 DATASHEET 5.2.3 Differential Driver Configuration The Differential Driver Configuration is a special case of the Backplane Mode. It is a dc coupled configuration recommended for applications like car-area networks or other cost-sensitive applications which do not require direct compatibility with existing ARCNET nodes and do not require isolation. The Differential Driver Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid Configuration. Like the Backplane Configuration, the Differential Driver Configuration does not isolate the node from the media. The Differential Driver interface includes a RS485 Driver/Receiver to transfer the data between the cable and the COM20022I. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is active. The nPULSE1 signal issues a 200nS (at 2.5Mbps) negative pulse to transmit a logic "1". Lack of pulse indicates a logic "0". The RXIN signal receives the data, the transmitter portion of the COM20022I is disabled during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive. 5.2.4 Programmable TXEN Polarity To accommodate transceivers with active high ENABLE pins, the COM20022I contains a programmable TXEN output. To program the TXEN pin for an active high pulse, the nPULSE2 pin should be connected to ground. To retain the normal active low polarity, nPULSE2 should be left open. The polarity determination is made at power on reset and is valid only for Backplane Mode operation. The nPULSE2 pin should remain grounded at all times if an active high polarity is desired. Figure 5.10 - Internal Block Diagram MICRO- SEQUENCER AND WORKING REGISTERS STATUS/ COMMAND REGISTER RESET LOGIC RECONFIGURATION TIMER NODE ID LOGIC OSCILLATOR TX/RX LOGIC ADDITIONAL REGISTERS ADDRESS DECODING CIRCUITRY 2K x 8 AD0-AD2, BUS ARBITRATION CIRCUITRY nPULSE1 nPULSE2 nTXEN nINTR nRESET RAM A0/nMUX A1 A2/BALE nRD/nDS nWR/DIR nCS D3-D15 RXIN nIOCS16 XTAL1 XTAL2 DMA DREQ nDACK TC nREFEX |
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