COM20022ITQFP datasheet(69/83 Pages) SMSC

69 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I

Page 69

Rev. 08-18-03

DATASHEET

Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle

A0-A2

VALID DATA

VALID

D0-D15

nCS

Note 2

nWR

nRD

t10

nIOCS16

VALID VALUE

t11

t12

t5**

Note 3

The Microcontroller typically accesses the COM20022 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20022 cycles.

Note 1:

Any cycle occurring after a write to Address Pointer Low Register requires a

minimum of 4TARB from the trailing edge of nWR to the leading edge of the

next nWR.

Note 2:

Write cycle for Address Pointer Low Register occurring after a write to Data

leading edge of the next nWR.

Notes 2 and 3 are applied to an access to Data Register by DMA transfer.

Note 3:

Write cycle for Address Pointer Low Register occurring after a read from Data

leading edge of nWR.

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

**** t11 is measured from the latest active (valid) timing among nCS, A0-A2.

t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.

*****

Data Hold from nWR High

nWR Low Width

nWR High Width

nRD

to nWR Low

nIOCS16 Output Delay from nCS Low

nIOCS16 Hold Delay from nCS High

t10

t11

t12

Parameter

Address Setup to nWR Active

nCS Setup to WR Active

Valid Data Setup to nWR High

min

max

4TARB

units

nCS Hold from nWR Inactive

Address Hold from nWR Inactive

Cycle Time (nWR

to Next

)

CASE 2: BUSTMG pin = LOW

0*****

40****

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