COM20022ITQFP datasheet(41/83 Pages) SMSC

41 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I

Page 41

Rev. 08-18-03

DATASHEET

Table 6.6 - Address Pointer High Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

Read Data

RDDATA

This bit tells the COM20022I whether the following access will be

a read or write. A logic "1" prepares the device for a read, a logic

"0" prepares it for a write.

Auto Increment

AUTOINC

This bit controls whether the address pointer will increment

automatically. A logic "1" on this bit allows automatic increment of

the pointer after each access, while a logic "0" disables this

function. Please refer to the Sequential Access Memory section

for further detail.

5-4

(Reserved)

These bits are undefined.

DMA Enable

DMAEN

This bit is used to Disable/Enable the assertion of the DMA

Request (DREQ pin) after writing the Address Pointer Low

assertion of the DREQ pin after writing the Address Pointer Low

the DREQ pin immediately. The DMA operation is terminated

immediately after the next DACK pin negation. The inverting

signal of DAMEN is the Interrupt source signal DMAEND. The

DMAEN bit is cleared automatically by finishing the DMA. If the

DMAEND bit in the Mask register is not masked, the Interrupt

occurs by finishing the DMA operation.

2-0

Address 10-8

A10-A8

These bits hold the upper three address bits which provide

addresses to RAM.

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