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COM20022ITQFP Datasheet(PDF) 24 Page - SMSC Corporation |
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COM20022ITQFP Datasheet(HTML) 24 Page - SMSC Corporation |
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24 / 83 page  10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet Rev. 08-18-03 Page 24 SMSC COM20022I DATASHEET The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration purposes. Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing The timing of the Burst mode DMA data transfer is found in the Timing Diagrams section of this data sheet. The basic sequence of operation is as follows: nDACK becomes active (low) upon DREQ becoming active (high) and catching the host bus (AEN= “1”). DREQ becomes inactive after TC asserts (when nDACK= “0”). In this case, DREQ doesn't become active again after nDACK becomes inactive. nDACK becomes inactive after DREQ= 0 and the present cycle finishes. The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration purposes. Figure 5.6 - Burst Mode DMA Data Transfer Rough Timing DREQ nDACK TC Read/Write Signal DREQ nDACK TC Read/Write Signal |
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