DDP3310B datasheet(46/60 Pages) MICRONAS

46 / 60 page

DDP 3310B

ADVANCE INFORMATION

Micronas

4.6.4.2. Line-locked Clock Inputs: LLC1, LLC2 (see Fig. 4–21)

4.6.4.3. Luma, Chroma Inputs (see Fig. 4–21)

Fig. 4–21: Line-locked clock input pins and luma/chroma bus input timing

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

VIL

Input Low Voltage

LLC1

LLC2

−−

0.8

VIH

Input High Voltage

2.0

−−

tSK

Clock skew

−−

±6ns

tR, tF

Clock Rise / Fall Time

−−

5ns

CIN

Input Capacitance

−

1/TLLC1

Clock Frequency

LLC1

12.0

−

17.2

MHz

tWL1

Clock Low Time

−−

tWH1

Clock High Time

−

1/TLLC2

Clock Frequency

LLC2

25.1

−

43.3

MHz

tWL2

Clock Low Time

−−

tWH2

Clock High Time

−−

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

VIL

Input Low Voltage

Y[0...7]

C[0...7]

−−

0.8

VIH

Input High Voltage

2.0

−−

tIS

Input Setup Time

−−

tIH

Input Hold Time

−−

CIN

Input Capacitance

−

Y,C Inputs

LLC2

tIS

tIH

LLC1

VIH

VIL

VIH

VIL

tSK

tR2

tF2

tWL2

tWH2

TLLC2

tWL1

tWH1

tR1

tF1

TLLC1

VIH

VIL

DDP3310B Datasheet(PDF) 46 Page - Micronas

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