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DDP3310B Datasheet(PDF) 25 Page - Micronas

Part # DDP3310B
Description  Display and Deflection Processor
PDF  60 Pages
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Manufacturer  MICRONAS [Micronas]
Direct Link  http://www.micronas.com
Logo MICRONAS - Micronas

DDP3310B Datasheet(HTML) 25 Page - Micronas

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ADVANCE INFORMATION
DDP 3310B
Micronas
25
CHROMA CHANNEL
h’1AF
16-r/w
luma/chroma matching delay
bit [2:0]
−2...2
variable chroma delay
bit [3]
not used, set to “0”
bit [4]
0/1
CB (U) sample first / CR (V) sample first
bit [5]
not used, set to “0”
0
0
0
CRCTRL
CDEL
ENVU
h’1AB
16-r/w
digital transient improvement
bit [3:0]
0..15
coring value
bit [7:4]
0..15
DTI gain
bit [8]
0/1
narrow/wide bandwidth mode
1
5
1
DTICTRL
DTICO
DTIGA
DTIMO
LUMA CHANNEL
h’1B1
16-r/w
bit [14:9]
0..63
picture contrast in steps of 1/32
32
CTM
h’19A
16-r/w
bit [8:0]
−256..255 luma DC-offset
0
BRM
h’1AA
16-r/w
luma peaking filter, the gain at high frequencies and small
signal amplitudes is: 1 + (k1+k2)/8
bit [3:0]
0..15
k1: peaking level undershoot
bit [7:4]
0..15
k2: peaking level overshoot
bit [8]
0/1
peaking value normal/inverted
(peaking/softening)
4
4
0
PK1
PKUN
PKOV
PKINV
h’1AE
16-r/w
luma peaking filter, coring
bit [4:0]
0..31
coring level
bit [7:5]
peaking reduction
000
100 %
001
80 %
01x
60 %
100
50 %
101
40 %
11x
30 %
bit [8]
0/1
peaking filter center frequency High/Low
3
0
0
PK2
COR
PKRD
PFS
h’18A
16-r/w
luma soft limiter, slope A and B
bit [3:0]
slope segment A
bit [7:4]
slope segment B
0
0
LSLS
LSLSA
LSLSB
h’18E
16-r/w
luma soft limiter, limit A
bit [7:0]
luma soft limiter absolute limit (unsigned)
bit [8]
0/1
modulation off/on
(resolution enhancement)
255
0
LSLA
LSLAL
LSLM
h’192
16-r/w
luma soft limiter, limit B
bit [8:0]
luma soft limiter segment B tilt point
(unsigned)
300
LSLTB
h’196
16-r/w
bit [8:0]
luma soft limiter segment A tilt point
(unsigned)
250
LSLTA
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name



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