DDP3310B datasheet(11/60 Pages) MICRONAS

11 / 60 page

FBL1/2

Peaking

Soft Limiter

CTI

digital

RGB

Matrix

Satu-

ration

SVM

×DAC

V, E/W

×DAC

RGB

Scan.

Vel. Mod.

Measu-

rement

ADC

RGB

out

RGB1

Sense

H-Flyb

HDrive

V & E/W

CrCb

4:2:2/4:1:1

FIFO

Write Ctrl

Line-locked

Clock

27/32 MHz

RSW1&2

×DAC

int. Bright.

×White-Drive

DAC

cutoff

×DAC

ext. Bright.

×White-Drive

×DAC

ext. Contr.

×White-drive

×BCL

Contrast

Intpl.

4:4:4

R,G,B

White-Dr.

× BCL

DAC

black

FBL

Prio

Clamp-

ing

Clamp-

ing

XDFP

– H-PLL2/3, flyback control

and soft start/stop

– vertical, E/W deflection

with EHT compensation

and vertical zoom

– beam current limiter

– cutoff & drive control loop

H-Drive

Gen.

H/V

Protection

Clk

Security

Scaler

FI-

Scaler

FI-

Scaler

H & V

Timing

H-Flyb.

Skew

RGB2

R,G,B

H/V Prot.

5 MHz

CLK

FI-

Cock

Generator

FI-

27/32 MHz

40.5/40.0 MHz

digital/analog

DAC

Picture

Frame

Gen.

Display

Frequency

Doubling

FIFO

Read Ctrl

13.5/16 MHz

H / V

I2C

Inter-

face

SDA/

SCL

dig. Bright.

int. H/V

Intpl.

4:2:2

Fig. 2–7: Detailed block diagram of the DDP 3310B

DDP3310B Datasheet(PDF) 11 Page - Micronas

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