DDP3310B datasheet(16/60 Pages) MICRONAS

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DDP 3310B

ADVANCE INFORMATION

Micronas

2.3. Synchronization and Deflection

2.3.1. Deflection Processing

The deflection processing generates the signals for the

horizontal and vertical drive (see Fig. 2–13). This block

contains two numeric phase-locked loops and a secu-

rity unit:

– PLL2 generates the horizontal and vertical timing,

e.g. blanking, clamping, and sync signals. Phase

and frequency are synchronized by the incoming

sync signals.

– PLL3 adjusts the phase of the horizontal drive pulse

and compensates for the delay of the horizontal out-

put stage.

– The security unit observes the H-Drive output sig-

nal. With an external 5-MHz reference clock, this

unit controls the H-Drive “off time” and period. In

case of an incorrect H-Drive signal the security unit

generates a free-running H-Drive signal divided

down from the 5-MHz reference clock.

The DDP 3310B is able to synchronize various hori-

zontal frequencies, even VGA frequencies. Allowed

horizontal frequencies are listed in Table 2–5. The hor-

izontal drive uses a high-voltage (8 V) open-drain out-

put transistor.

2.3.2. Security Unit for H-Drive

The security unit observes the H-Drive output signal

with an external 5-MHz reference clock. For different

horizontal frequencies the security unit uses different

ranges to control the H-Drive signal. Selecting a spe-

cific horizontal frequency via I2C-register HFREQ

automatically switches to the corresponding security

range. The control ranges are listed in Table 2–5.

The window of the control range has to fit into a main

control window which is selectable with the FREQSEL

input pin. With a Low signal at this pin, the main control

range is 28.8… 34.4

µs and with a High signal, the

main control range is 25.6…29.2

µs. This is to prevent

malfunctions if the horizontal deflection stage is pre-

pared for VGA frequencies.

The Horizontal Drive Output can be forced to the High

level during Flyback. This means, the falling edge of

the drive pulse occurs at the earliest to the end of the

flyback pulse. This function can be enabled via the I2C

bus (EFLB).

Fig. 2–13: Deflection processing block diagram

Phase

Comparator

Low-Pass

PLL2

E/W

Correction

Sawtooth

PWM

15-Bit

E/W

Output

V+

Output

PWM

15-Bit

DCO

HSYNC

Phase

Comparator

Low-Pass

PLL3

Flyback

DCO

Display

Timing

Blanking, Clamping, etc.

Clock & Control

Horizontal

Generator

Vertical Reset

VSYNC

−

Security

Unit

Drive

FREQSEL

1H or 2H

1V or 2V

FIFORWR

FIFOWR

FIFORRD

FIFORD

FIFO control

Drive

Display

Frequency

Doubling

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