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MYX29GL01GS11DPIV2 Datasheet(PDF) 53 Page - Micross Components |
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MYX29GL01GS11DPIV2 Datasheet(HTML) 53 Page - Micross Components |
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53 / 68 page  MYX29GL01GS11DPIV2 Revision 1.0 - 01/26/2015 *Advanced information. Subject to change without notice. 53 1Gb GL-S MirrorBit® Eclipse™ Flash Memory MYX29GL01GS11DPIV2* Form #: CSI-D-685 Document 001 Figure 9: Power-Up Diagram 78 GL-S MirrorBit® Family S29GL_128S_01GS_00_08 October 9, 2013 D a t a S h e e t 10.3 Power-On Reset (POR) and Warm Reset Normal precautions must be taken for supply decoupling to stabilize the VCC and VIO power supplies. Each device in a system should have the VCC and VIO power supplies decoupled by a suitable capacitor close to the package connections (this capacitor is generally on the order of 0.1 µF). Notes: 1. Not 100% tested. 2. Timing measured from VCC reaching VCC minimum and VIO reaching VIO minimum to VIH on Reset and VIL on CE#. 3. RESET# Low is optional during POR. If RESET is asserted during POR, the later of tRPH, tVIOS, or tVCS will determine when CE# may go Low. If RESET# remains Low after tVIOS, or tVCS is satisfied, tRPH is measured from the end of tVIOS, or tVCS. RESET must also be High tRH before CE# goes Low. 4. VCC ≥ VIO - 200 mV during power-up. 5. VCC and VIO ramp rate can be non-linear. 6. Sum of tRP and tRH must be equal to or greater than tRPH. 10.3.1 Power-On (Cold) Reset (POR) During the rise of power supplies the VIO supply voltage must remain less than or equal to the VCC supply voltage. VIH also must remain less than or equal to the VIO supply. The Cold Reset Embedded Algorithm requires a relatively long, hundreds of µs, period (tVCS) to load all of the EAC algorithms and default state from non-volatile memory. During the Cold Reset period all control signals including CE# and RESET# are ignored. If CE# is Low during tVCS the device may draw higher than normal POR current during tVCS but the level of CE# will not affect the Cold Reset EA. CE# or OE# must transition from High to Low after tVCS for a valid read or write operation. RESET# may be High or Low during tVCS. If RESET# is Low during tVCS it may remain Low at the end of tVCS to hold the device in the Hardware Reset state. If RESET# is High at the end of tVCS the device will go to the Standby state. When power is first applied, with supply voltage below VRST then rising to reach operating range minimum, internal device configuration and warm reset activities are initiated. CE# is ignored for the duration of the POR operation (tVCS or tVIOS). RESET# Low during this POR period is optional. If RESET# is driven Low during POR it must satisfy the Hardware Reset parameters tRP and tRPH. In which case the Reset operations will be completed at the later of tVCS or tVIOS or tRPH. During Cold Reset the device will draw ICC7 current. Figure 10.3 Power-Up Diagram Table 10.2 Power ON and Reset Parameters Parameter Description Limit Value Unit tVCS VCC Setup Time to first access (Notes 1, 2) Min 300 µs tVIOS VIO Setup Time to first access (Notes 1, 2) Min 300 µs tRPH RESET# Low to CE# Low Min 35 µs tRP RESET# Pulse Width Min 200 ns tRH Time between RESET# (High) and CE# (low) Min 50 ns tCEH CE# Pulse Width High Min 20 ns VCC VIO RESET# CE# tRH tVIOS tVCS tCEH 10.2.2 Hardware (Warm) Reset DuringHardwareReset(tRPH)thedevicewilldrawICC5current. WhenRESET#continuestobeheldatVSS,thedevicedrawsCMOSstandbycurrent(ICC4).IfRESET#isheld atVIL,butnotatVSS,thestandbycurrentisgreater. IfaColdResethasnotbeencompletedbythedevicewhenRESET#isassertedLowaftertVCS,theCold Reset#EAwillbeperformedinsteadoftheWarmRESET#,requiringtVCStimetocomplete. SeeFigure10:HardwareReset(page54). AfterthedevicehascompletedPORandenteredtheStandbystate,anylatertransitiontotheHardwareReset statewillinitiatetheWarmResetEmbeddedAlgorithm.AWarmResetismuchshorterthanaColdReset, taking tens of μs (tRPH) to complete. During the Warm Reset EA, any in progress Embedded Algorithm is stoppedandtheEACisreturnedtoitsPORstatewithoutreloadingEACalgorithmsfromnon-volatilememory. AftertheWarmResetEAcompletes,theinterfacewillremainintheHardwareResetstateifRESET#remains Low.WhenRESET#returnsHightheinterfacewilltransittotheStandbystate.IfRESET#isHighattheendof theWarmResetEA,theinterfacewilldirectlytransittotheStandbystate. IfPORhasnotbeenproperlycompletedbytheendoftVCS,alatertransitiontotheHardwareResetstatewill causeatransitiontothePower-onResetinterfacestateandinitiatetheColdResetEmbeddedAlgorithm.This ensuresthedevicecancompleteaColdResetevenifsomeaspectofthesystemPower-Onvoltageramp-up causesthePORtonotinitiateorcompletecorrectly.TheRY/BY#pinisLowduringcoldorwarmresetasan indicationthatthedeviceisbusyperformingresetoperations.HardwareResetisinitiatedbytheRESET#signal goingtoVIL. |
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